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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wenyou Yang2c62c562015-11-04 14:25:13 +08002/*
3 * Atmel PIO4 device driver
4 *
5 * Copyright (C) 2015 Atmel Corporation
6 * Wenyou.Yang <wenyou.yang@atmel.com>
Wenyou Yang2c62c562015-11-04 14:25:13 +08007 */
8#include <common.h>
Wenyou Yangee3311d2016-07-20 17:16:26 +08009#include <clk.h>
Wenyou Yang2c62c562015-11-04 14:25:13 +080010#include <dm.h>
Wenyou Yangee3311d2016-07-20 17:16:26 +080011#include <fdtdec.h>
Simon Glass336d4612020-02-03 07:36:16 -070012#include <malloc.h>
Wenyou Yang2c62c562015-11-04 14:25:13 +080013#include <asm/arch/hardware.h>
Wenyou Yangee3311d2016-07-20 17:16:26 +080014#include <asm/gpio.h>
Simon Glasscd93d622020-05-10 11:40:13 -060015#include <linux/bitops.h>
Wenyou Yang2c62c562015-11-04 14:25:13 +080016#include <mach/gpio.h>
17#include <mach/atmel_pio4.h>
18
Wenyou Yangee3311d2016-07-20 17:16:26 +080019DECLARE_GLOBAL_DATA_PTR;
20
Wenyou Yang2c62c562015-11-04 14:25:13 +080021static struct atmel_pio4_port *atmel_pio4_port_base(u32 port)
22{
23 struct atmel_pio4_port *base = NULL;
24
25 switch (port) {
26 case AT91_PIO_PORTA:
27 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOA;
28 break;
29 case AT91_PIO_PORTB:
30 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOB;
31 break;
32 case AT91_PIO_PORTC:
33 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOC;
34 break;
35 case AT91_PIO_PORTD:
36 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD;
37 break;
38 default:
39 printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n",
40 port);
41 break;
42 }
43
44 return base;
45}
46
47static int atmel_pio4_config_io_func(u32 port, u32 pin,
Ludovic Desroches8ee54672018-04-24 10:16:01 +030048 u32 func, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +080049{
50 struct atmel_pio4_port *port_base;
51 u32 reg, mask;
52
Wenyou Yang46ed9382016-07-20 17:16:25 +080053 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
Simon Glass7c843192017-09-17 16:54:53 -060054 return -EINVAL;
Wenyou Yang2c62c562015-11-04 14:25:13 +080055
56 port_base = atmel_pio4_port_base(port);
57 if (!port_base)
Simon Glass7c843192017-09-17 16:54:53 -060058 return -EINVAL;
Wenyou Yang2c62c562015-11-04 14:25:13 +080059
60 mask = 1 << pin;
61 reg = func;
Ludovic Desroches8ee54672018-04-24 10:16:01 +030062 reg |= config;
Wenyou Yang2c62c562015-11-04 14:25:13 +080063
64 writel(mask, &port_base->mskr);
65 writel(reg, &port_base->cfgr);
66
67 return 0;
68}
69
Ludovic Desroches8ee54672018-04-24 10:16:01 +030070int atmel_pio4_set_gpio(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +080071{
72 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +080073 ATMEL_PIO_CFGR_FUNC_GPIO,
Ludovic Desroches8ee54672018-04-24 10:16:01 +030074 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +080075}
76
Ludovic Desroches8ee54672018-04-24 10:16:01 +030077int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +080078{
79 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +080080 ATMEL_PIO_CFGR_FUNC_PERIPH_A,
Ludovic Desroches8ee54672018-04-24 10:16:01 +030081 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +080082}
83
Ludovic Desroches8ee54672018-04-24 10:16:01 +030084int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +080085{
86 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +080087 ATMEL_PIO_CFGR_FUNC_PERIPH_B,
Ludovic Desroches8ee54672018-04-24 10:16:01 +030088 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +080089}
90
Ludovic Desroches8ee54672018-04-24 10:16:01 +030091int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +080092{
93 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +080094 ATMEL_PIO_CFGR_FUNC_PERIPH_C,
Ludovic Desroches8ee54672018-04-24 10:16:01 +030095 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +080096}
97
Ludovic Desroches8ee54672018-04-24 10:16:01 +030098int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +080099{
100 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +0800101 ATMEL_PIO_CFGR_FUNC_PERIPH_D,
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300102 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800103}
104
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300105int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +0800106{
107 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +0800108 ATMEL_PIO_CFGR_FUNC_PERIPH_E,
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300109 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800110}
111
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300112int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +0800113{
114 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +0800115 ATMEL_PIO_CFGR_FUNC_PERIPH_F,
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300116 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800117}
118
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300119int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 config)
Wenyou Yang2c62c562015-11-04 14:25:13 +0800120{
121 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +0800122 ATMEL_PIO_CFGR_FUNC_PERIPH_G,
Ludovic Desroches8ee54672018-04-24 10:16:01 +0300123 config);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800124}
125
126int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value)
127{
128 struct atmel_pio4_port *port_base;
129 u32 reg, mask;
130
Wenyou Yang46ed9382016-07-20 17:16:25 +0800131 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
Simon Glass7c843192017-09-17 16:54:53 -0600132 return -EINVAL;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800133
134 port_base = atmel_pio4_port_base(port);
135 if (!port_base)
Simon Glass7c843192017-09-17 16:54:53 -0600136 return -EINVAL;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800137
138 mask = 0x01 << pin;
Wenyou Yang46ed9382016-07-20 17:16:25 +0800139 reg = ATMEL_PIO_CFGR_FUNC_GPIO | ATMEL_PIO_DIR_MASK;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800140
141 writel(mask, &port_base->mskr);
142 writel(reg, &port_base->cfgr);
143
144 if (value)
145 writel(mask, &port_base->sodr);
146 else
147 writel(mask, &port_base->codr);
148
149 return 0;
150}
151
152int atmel_pio4_get_pio_input(u32 port, u32 pin)
153{
154 struct atmel_pio4_port *port_base;
155 u32 reg, mask;
156
Wenyou Yang46ed9382016-07-20 17:16:25 +0800157 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
Simon Glass7c843192017-09-17 16:54:53 -0600158 return -EINVAL;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800159
160 port_base = atmel_pio4_port_base(port);
161 if (!port_base)
Simon Glass7c843192017-09-17 16:54:53 -0600162 return -EINVAL;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800163
164 mask = 0x01 << pin;
Wenyou Yang46ed9382016-07-20 17:16:25 +0800165 reg = ATMEL_PIO_CFGR_FUNC_GPIO;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800166
167 writel(mask, &port_base->mskr);
168 writel(reg, &port_base->cfgr);
169
170 return (readl(&port_base->pdsr) & mask) ? 1 : 0;
171}
172
Simon Glassbcee8d62019-12-06 21:41:35 -0700173#if CONFIG_IS_ENABLED(DM_GPIO)
Wenyou Yangee3311d2016-07-20 17:16:26 +0800174
175struct atmel_pioctrl_data {
176 u32 nbanks;
177};
178
Simon Glass8a8d24b2020-12-03 16:55:23 -0700179struct atmel_pio4_plat {
Wenyou Yangee3311d2016-07-20 17:16:26 +0800180 struct atmel_pio4_port *reg_base;
181};
182
183static struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
184 u32 bank)
185{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700186 struct atmel_pio4_plat *plat = dev_get_plat(dev);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800187 struct atmel_pio4_port *port_base =
188 (struct atmel_pio4_port *)((u32)plat->reg_base +
189 ATMEL_PIO_BANK_OFFSET * bank);
190
191 return port_base;
192}
193
Wenyou Yang2c62c562015-11-04 14:25:13 +0800194static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset)
195{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800196 u32 bank = ATMEL_PIO_BANK(offset);
197 u32 line = ATMEL_PIO_LINE(offset);
198 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
199 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800200
201 writel(mask, &port_base->mskr);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800202
203 clrbits_le32(&port_base->cfgr,
204 ATMEL_PIO_CFGR_FUNC_MASK | ATMEL_PIO_DIR_MASK);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800205
206 return 0;
207}
208
209static int atmel_pio4_direction_output(struct udevice *dev,
210 unsigned offset, int value)
211{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800212 u32 bank = ATMEL_PIO_BANK(offset);
213 u32 line = ATMEL_PIO_LINE(offset);
214 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
215 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800216
217 writel(mask, &port_base->mskr);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800218
219 clrsetbits_le32(&port_base->cfgr,
220 ATMEL_PIO_CFGR_FUNC_MASK, ATMEL_PIO_DIR_MASK);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800221
222 if (value)
223 writel(mask, &port_base->sodr);
224 else
225 writel(mask, &port_base->codr);
226
227 return 0;
228}
229
230static int atmel_pio4_get_value(struct udevice *dev, unsigned offset)
231{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800232 u32 bank = ATMEL_PIO_BANK(offset);
233 u32 line = ATMEL_PIO_LINE(offset);
234 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
235 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800236
237 return (readl(&port_base->pdsr) & mask) ? 1 : 0;
238}
239
240static int atmel_pio4_set_value(struct udevice *dev,
241 unsigned offset, int value)
242{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800243 u32 bank = ATMEL_PIO_BANK(offset);
244 u32 line = ATMEL_PIO_LINE(offset);
245 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
246 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800247
248 if (value)
249 writel(mask, &port_base->sodr);
250 else
251 writel(mask, &port_base->codr);
252
253 return 0;
254}
255
256static int atmel_pio4_get_function(struct udevice *dev, unsigned offset)
257{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800258 u32 bank = ATMEL_PIO_BANK(offset);
259 u32 line = ATMEL_PIO_LINE(offset);
260 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
261 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800262
263 writel(mask, &port_base->mskr);
264
265 return (readl(&port_base->cfgr) &
Wenyou Yang46ed9382016-07-20 17:16:25 +0800266 ATMEL_PIO_DIR_MASK) ? GPIOF_OUTPUT : GPIOF_INPUT;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800267}
268
269static const struct dm_gpio_ops atmel_pio4_ops = {
270 .direction_input = atmel_pio4_direction_input,
271 .direction_output = atmel_pio4_direction_output,
272 .get_value = atmel_pio4_get_value,
273 .set_value = atmel_pio4_set_value,
274 .get_function = atmel_pio4_get_function,
275};
276
Wenyou Yangee3311d2016-07-20 17:16:26 +0800277static int atmel_pio4_bind(struct udevice *dev)
278{
Simon Glass79fc0c72017-05-17 17:18:06 -0600279 return dm_scan_fdt_dev(dev);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800280}
281
Wenyou Yang2c62c562015-11-04 14:25:13 +0800282static int atmel_pio4_probe(struct udevice *dev)
283{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700284 struct atmel_pio4_plat *plat = dev_get_plat(dev);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800285 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800286 struct atmel_pioctrl_data *pioctrl_data;
Wenyou Yangee3311d2016-07-20 17:16:26 +0800287 struct clk clk;
288 fdt_addr_t addr_base;
289 u32 nbanks;
Wenyou Yangee3311d2016-07-20 17:16:26 +0800290 int ret;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800291
Wenyou Yangee3311d2016-07-20 17:16:26 +0800292 ret = clk_get_by_index(dev, 0, &clk);
293 if (ret)
294 return ret;
295
Wenyou Yangee3311d2016-07-20 17:16:26 +0800296 ret = clk_enable(&clk);
297 if (ret)
298 return ret;
299
300 clk_free(&clk);
301
Masahiro Yamada25484932020-07-17 14:36:48 +0900302 addr_base = dev_read_addr(dev);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800303 if (addr_base == FDT_ADDR_T_NONE)
304 return -EINVAL;
305
306 plat->reg_base = (struct atmel_pio4_port *)addr_base;
307
308 pioctrl_data = (struct atmel_pioctrl_data *)dev_get_driver_data(dev);
309 nbanks = pioctrl_data->nbanks;
310
Simon Glasse160f7d2017-01-17 16:52:55 -0700311 uc_priv->bank_name = fdt_get_name(gd->fdt_blob, dev_of_offset(dev),
312 NULL);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800313 uc_priv->gpio_count = nbanks * ATMEL_PIO_NPINS_PER_BANK;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800314
315 return 0;
316}
317
Wenyou Yangee3311d2016-07-20 17:16:26 +0800318/*
319 * The number of banks can be different from a SoC to another one.
320 * We can have up to 16 banks.
321 */
322static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
323 .nbanks = 4,
324};
325
326static const struct udevice_id atmel_pio4_ids[] = {
327 {
328 .compatible = "atmel,sama5d2-gpio",
329 .data = (ulong)&atmel_sama5d2_pioctrl_data,
330 },
331 {}
332};
333
Wenyou Yang2c62c562015-11-04 14:25:13 +0800334U_BOOT_DRIVER(gpio_atmel_pio4) = {
335 .name = "gpio_atmel_pio4",
336 .id = UCLASS_GPIO,
337 .ops = &atmel_pio4_ops,
338 .probe = atmel_pio4_probe,
Wenyou Yangee3311d2016-07-20 17:16:26 +0800339 .bind = atmel_pio4_bind,
340 .of_match = atmel_pio4_ids,
Simon Glass8a8d24b2020-12-03 16:55:23 -0700341 .plat_auto = sizeof(struct atmel_pio4_plat),
Wenyou Yang2c62c562015-11-04 14:25:13 +0800342};
Wenyou Yangee3311d2016-07-20 17:16:26 +0800343
Wenyou Yang2c62c562015-11-04 14:25:13 +0800344#endif