Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Broadcom PHY drivers |
| 3 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 5 | * |
| 6 | * Copyright 2010-2011 Freescale Semiconductor, Inc. |
| 7 | * author Andy Fleming |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 8 | */ |
| 9 | #include <config.h> |
| 10 | #include <common.h> |
| 11 | #include <phy.h> |
| 12 | |
| 13 | /* Broadcom BCM54xx -- taken from linux sungem_phy */ |
| 14 | #define MIIM_BCM54xx_AUXCNTL 0x18 |
| 15 | #define MIIM_BCM54xx_AUXCNTL_ENCODE(val) (((val & 0x7) << 12)|(val & 0x7)) |
| 16 | #define MIIM_BCM54xx_AUXSTATUS 0x19 |
| 17 | #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700 |
| 18 | #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8 |
| 19 | |
| 20 | #define MIIM_BCM54XX_SHD 0x1c |
| 21 | #define MIIM_BCM54XX_SHD_WRITE 0x8000 |
| 22 | #define MIIM_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10) |
| 23 | #define MIIM_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0) |
| 24 | #define MIIM_BCM54XX_SHD_WR_ENCODE(val, data) \ |
| 25 | (MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \ |
| 26 | MIIM_BCM54XX_SHD_DATA(data)) |
| 27 | |
| 28 | #define MIIM_BCM54XX_EXP_DATA 0x15 /* Expansion register data */ |
| 29 | #define MIIM_BCM54XX_EXP_SEL 0x17 /* Expansion register select */ |
| 30 | #define MIIM_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */ |
| 31 | #define MIIM_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */ |
| 32 | |
| 33 | /* Broadcom BCM5461S */ |
| 34 | static int bcm5461_config(struct phy_device *phydev) |
| 35 | { |
| 36 | genphy_config_aneg(phydev); |
| 37 | |
| 38 | phy_reset(phydev); |
| 39 | |
| 40 | return 0; |
| 41 | } |
| 42 | |
| 43 | static int bcm54xx_parse_status(struct phy_device *phydev) |
| 44 | { |
| 45 | unsigned int mii_reg; |
| 46 | |
| 47 | mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXSTATUS); |
| 48 | |
| 49 | switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> |
| 50 | MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) { |
| 51 | case 1: |
| 52 | phydev->duplex = DUPLEX_HALF; |
| 53 | phydev->speed = SPEED_10; |
| 54 | break; |
| 55 | case 2: |
| 56 | phydev->duplex = DUPLEX_FULL; |
| 57 | phydev->speed = SPEED_10; |
| 58 | break; |
| 59 | case 3: |
| 60 | phydev->duplex = DUPLEX_HALF; |
| 61 | phydev->speed = SPEED_100; |
| 62 | break; |
| 63 | case 5: |
| 64 | phydev->duplex = DUPLEX_FULL; |
| 65 | phydev->speed = SPEED_100; |
| 66 | break; |
| 67 | case 6: |
| 68 | phydev->duplex = DUPLEX_HALF; |
| 69 | phydev->speed = SPEED_1000; |
| 70 | break; |
| 71 | case 7: |
| 72 | phydev->duplex = DUPLEX_FULL; |
| 73 | phydev->speed = SPEED_1000; |
| 74 | break; |
| 75 | default: |
| 76 | printf("Auto-neg error, defaulting to 10BT/HD\n"); |
| 77 | phydev->duplex = DUPLEX_HALF; |
| 78 | phydev->speed = SPEED_10; |
| 79 | break; |
| 80 | } |
| 81 | |
| 82 | return 0; |
| 83 | } |
| 84 | |
| 85 | static int bcm54xx_startup(struct phy_device *phydev) |
| 86 | { |
| 87 | /* Read the Status (2x to make sure link is right) */ |
| 88 | genphy_update_link(phydev); |
| 89 | bcm54xx_parse_status(phydev); |
| 90 | |
| 91 | return 0; |
| 92 | } |
| 93 | |
| 94 | /* Broadcom BCM5482S */ |
| 95 | /* |
| 96 | * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain |
| 97 | * circumstances. eg a gigabit TSEC connected to a gigabit switch with |
| 98 | * a 4-wire ethernet cable. Both ends advertise gigabit, but can't |
| 99 | * link. "Ethernet@Wirespeed" reduces advertised speed until link |
| 100 | * can be achieved. |
| 101 | */ |
| 102 | static u32 bcm5482_read_wirespeed(struct phy_device *phydev, u32 reg) |
| 103 | { |
| 104 | return (phy_read(phydev, MDIO_DEVAD_NONE, reg) & 0x8FFF) | 0x8010; |
| 105 | } |
| 106 | |
| 107 | static int bcm5482_config(struct phy_device *phydev) |
| 108 | { |
| 109 | unsigned int reg; |
| 110 | |
| 111 | /* reset the PHY */ |
| 112 | reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); |
| 113 | reg |= BMCR_RESET; |
| 114 | phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); |
| 115 | |
| 116 | /* Setup read from auxilary control shadow register 7 */ |
| 117 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, |
| 118 | MIIM_BCM54xx_AUXCNTL_ENCODE(7)); |
| 119 | /* Read Misc Control register and or in Ethernet@Wirespeed */ |
| 120 | reg = bcm5482_read_wirespeed(phydev, MIIM_BCM54xx_AUXCNTL); |
| 121 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg); |
| 122 | |
| 123 | /* Initial config/enable of secondary SerDes interface */ |
| 124 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, |
| 125 | MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf)); |
| 126 | /* Write intial value to secondary SerDes Contol */ |
| 127 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, |
| 128 | MIIM_BCM54XX_EXP_SEL_SSD | 0); |
| 129 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, |
| 130 | BMCR_ANRESTART); |
| 131 | /* Enable copper/fiber auto-detect */ |
| 132 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, |
| 133 | MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201)); |
| 134 | |
| 135 | genphy_config_aneg(phydev); |
| 136 | |
| 137 | return 0; |
| 138 | } |
| 139 | |
| 140 | /* |
| 141 | * Find out if PHY is in copper or serdes mode by looking at Expansion Reg |
| 142 | * 0x42 - "Operating Mode Status Register" |
| 143 | */ |
| 144 | static int bcm5482_is_serdes(struct phy_device *phydev) |
| 145 | { |
| 146 | u16 val; |
| 147 | int serdes = 0; |
| 148 | |
| 149 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, |
| 150 | MIIM_BCM54XX_EXP_SEL_ER | 0x42); |
| 151 | val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA); |
| 152 | |
| 153 | switch (val & 0x1f) { |
| 154 | case 0x0d: /* RGMII-to-100Base-FX */ |
| 155 | case 0x0e: /* RGMII-to-SGMII */ |
| 156 | case 0x0f: /* RGMII-to-SerDes */ |
| 157 | case 0x12: /* SGMII-to-SerDes */ |
| 158 | case 0x13: /* SGMII-to-100Base-FX */ |
| 159 | case 0x16: /* SerDes-to-Serdes */ |
| 160 | serdes = 1; |
| 161 | break; |
| 162 | case 0x6: /* RGMII-to-Copper */ |
| 163 | case 0x14: /* SGMII-to-Copper */ |
| 164 | case 0x17: /* SerDes-to-Copper */ |
| 165 | break; |
| 166 | default: |
| 167 | printf("ERROR, invalid PHY mode (0x%x\n)", val); |
| 168 | break; |
| 169 | } |
| 170 | |
| 171 | return serdes; |
| 172 | } |
| 173 | |
| 174 | /* |
| 175 | * Determine SerDes link speed and duplex from Expansion reg 0x42 "Operating |
| 176 | * Mode Status Register" |
| 177 | */ |
| 178 | static u32 bcm5482_parse_serdes_sr(struct phy_device *phydev) |
| 179 | { |
| 180 | u16 val; |
| 181 | int i = 0; |
| 182 | |
| 183 | /* Wait 1s for link - Clause 37 autonegotiation happens very fast */ |
| 184 | while (1) { |
| 185 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, |
| 186 | MIIM_BCM54XX_EXP_SEL_ER | 0x42); |
| 187 | val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA); |
| 188 | |
| 189 | if (val & 0x8000) |
| 190 | break; |
| 191 | |
| 192 | if (i++ > 1000) { |
| 193 | phydev->link = 0; |
| 194 | return 1; |
| 195 | } |
| 196 | |
| 197 | udelay(1000); /* 1 ms */ |
| 198 | } |
| 199 | |
| 200 | phydev->link = 1; |
| 201 | switch ((val >> 13) & 0x3) { |
| 202 | case (0x00): |
| 203 | phydev->speed = 10; |
| 204 | break; |
| 205 | case (0x01): |
| 206 | phydev->speed = 100; |
| 207 | break; |
| 208 | case (0x02): |
| 209 | phydev->speed = 1000; |
| 210 | break; |
| 211 | } |
| 212 | |
| 213 | phydev->duplex = (val & 0x1000) == 0x1000; |
| 214 | |
| 215 | return 0; |
| 216 | } |
| 217 | |
| 218 | /* |
| 219 | * Figure out if BCM5482 is in serdes or copper mode and determine link |
| 220 | * configuration accordingly |
| 221 | */ |
| 222 | static int bcm5482_startup(struct phy_device *phydev) |
| 223 | { |
| 224 | if (bcm5482_is_serdes(phydev)) { |
| 225 | bcm5482_parse_serdes_sr(phydev); |
| 226 | phydev->port = PORT_FIBRE; |
| 227 | } else { |
| 228 | /* Wait for auto-negotiation to complete or fail */ |
| 229 | genphy_update_link(phydev); |
| 230 | /* Parse BCM54xx copper aux status register */ |
| 231 | bcm54xx_parse_status(phydev); |
| 232 | } |
| 233 | |
| 234 | return 0; |
| 235 | } |
| 236 | |
| 237 | static struct phy_driver BCM5461S_driver = { |
| 238 | .name = "Broadcom BCM5461S", |
| 239 | .uid = 0x2060c0, |
| 240 | .mask = 0xfffff0, |
| 241 | .features = PHY_GBIT_FEATURES, |
| 242 | .config = &bcm5461_config, |
| 243 | .startup = &bcm54xx_startup, |
| 244 | .shutdown = &genphy_shutdown, |
| 245 | }; |
| 246 | |
| 247 | static struct phy_driver BCM5464S_driver = { |
| 248 | .name = "Broadcom BCM5464S", |
| 249 | .uid = 0x2060b0, |
| 250 | .mask = 0xfffff0, |
| 251 | .features = PHY_GBIT_FEATURES, |
| 252 | .config = &bcm5461_config, |
| 253 | .startup = &bcm54xx_startup, |
| 254 | .shutdown = &genphy_shutdown, |
| 255 | }; |
| 256 | |
| 257 | static struct phy_driver BCM5482S_driver = { |
| 258 | .name = "Broadcom BCM5482S", |
| 259 | .uid = 0x143bcb0, |
| 260 | .mask = 0xffffff0, |
| 261 | .features = PHY_GBIT_FEATURES, |
| 262 | .config = &bcm5482_config, |
| 263 | .startup = &bcm5482_startup, |
| 264 | .shutdown = &genphy_shutdown, |
| 265 | }; |
| 266 | |
| 267 | int phy_broadcom_init(void) |
| 268 | { |
| 269 | phy_register(&BCM5482S_driver); |
| 270 | phy_register(&BCM5464S_driver); |
| 271 | phy_register(&BCM5461S_driver); |
| 272 | |
| 273 | return 0; |
| 274 | } |