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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek194846f2012-09-14 00:55:24 +00002/*
3 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
Michal Simek194846f2012-09-14 00:55:24 +00005 */
6
Michal Simek59da82e2016-07-14 14:40:03 +02007#include <clk.h>
Michal Simek194846f2012-09-14 00:55:24 +00008#include <common.h>
Simon Glass42800ff2015-10-17 19:41:27 -06009#include <debug_uart.h>
10#include <dm.h>
Simon Glassc54c0a42015-10-17 19:41:22 -060011#include <errno.h>
Michal Simekc9416b92014-02-24 11:16:33 +010012#include <fdtdec.h>
Michal Simek194846f2012-09-14 00:55:24 +000013#include <watchdog.h>
14#include <asm/io.h>
Simon Glass336d4612020-02-03 07:36:16 -070015#include <dm/device_compat.h>
Michal Simek194846f2012-09-14 00:55:24 +000016#include <linux/compiler.h>
17#include <serial.h>
Simon Glass61b29b82020-02-03 07:36:15 -070018#include <linux/err.h>
Michal Simek194846f2012-09-14 00:55:24 +000019
Michal Simekc9a2c472018-06-14 11:13:41 +020020#define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */
Michal Simeke90d2652018-06-14 09:43:34 +020021#define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */
Michal Simekc9a2c472018-06-14 11:13:41 +020022#define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */
Michal Simek194846f2012-09-14 00:55:24 +000023
Michal Simekc9a2c472018-06-14 11:13:41 +020024#define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */
25#define ZYNQ_UART_CR_RX_EN BIT(2) /* RX enabled */
26#define ZYNQ_UART_CR_TXRST BIT(1) /* TX logic reset */
27#define ZYNQ_UART_CR_RXRST BIT(0) /* RX logic reset */
Michal Simek194846f2012-09-14 00:55:24 +000028
29#define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
30
Michal Simek194846f2012-09-14 00:55:24 +000031struct uart_zynq {
Michal Simeka2425e62015-01-07 15:00:47 +010032 u32 control; /* 0x0 - Control Register [8:0] */
33 u32 mode; /* 0x4 - Mode Register [10:0] */
Michal Simek194846f2012-09-14 00:55:24 +000034 u32 reserved1[4];
Michal Simeka2425e62015-01-07 15:00:47 +010035 u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */
Michal Simek194846f2012-09-14 00:55:24 +000036 u32 reserved2[4];
Michal Simeka2425e62015-01-07 15:00:47 +010037 u32 channel_sts; /* 0x2c - Channel Status [11:0] */
38 u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */
39 u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
Michal Simek194846f2012-09-14 00:55:24 +000040};
41
Michal Simek6bdf0a92018-06-14 10:32:27 +020042struct zynq_uart_platdata {
Simon Glass42800ff2015-10-17 19:41:27 -060043 struct uart_zynq *regs;
Michal Simek194846f2012-09-14 00:55:24 +000044};
45
Michal Simek895a7862020-03-24 11:31:42 +010046/* Set up the baud rate */
Simon Glassc54c0a42015-10-17 19:41:22 -060047static void _uart_zynq_serial_setbrg(struct uart_zynq *regs,
48 unsigned long clock, unsigned long baud)
Michal Simek194846f2012-09-14 00:55:24 +000049{
50 /* Calculation results. */
51 unsigned int calc_bauderror, bdiv, bgen;
52 unsigned long calc_baud = 0;
Michal Simek194846f2012-09-14 00:55:24 +000053
Michal Simek04bc5c92015-04-15 13:05:06 +020054 /* Covering case where input clock is so slow */
Simon Glassc54c0a42015-10-17 19:41:22 -060055 if (clock < 1000000 && baud > 4800)
56 baud = 4800;
Michal Simek04bc5c92015-04-15 13:05:06 +020057
Michal Simek194846f2012-09-14 00:55:24 +000058 /* master clock
59 * Baud rate = ------------------
60 * bgen * (bdiv + 1)
61 *
62 * Find acceptable values for baud generation.
63 */
64 for (bdiv = 4; bdiv < 255; bdiv++) {
65 bgen = clock / (baud * (bdiv + 1));
66 if (bgen < 2 || bgen > 65535)
67 continue;
68
69 calc_baud = clock / (bgen * (bdiv + 1));
70
71 /*
72 * Use first calculated baudrate with
73 * an acceptable (<3%) error
74 */
75 if (baud > calc_baud)
76 calc_bauderror = baud - calc_baud;
77 else
78 calc_bauderror = calc_baud - baud;
79 if (((calc_bauderror * 100) / baud) < 3)
80 break;
81 }
82
83 writel(bdiv, &regs->baud_rate_divider);
84 writel(bgen, &regs->baud_rate_gen);
85}
86
Simon Glassc54c0a42015-10-17 19:41:22 -060087/* Initialize the UART, with...some settings. */
88static void _uart_zynq_serial_init(struct uart_zynq *regs)
89{
90 /* RX/TX enabled & reset */
91 writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
92 ZYNQ_UART_CR_RXRST, &regs->control);
93 writel(ZYNQ_UART_MR_PARITY_NONE, &regs->mode); /* 8 bit, no parity */
94}
95
Simon Glassc54c0a42015-10-17 19:41:22 -060096static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
97{
Michal Simeke90d2652018-06-14 09:43:34 +020098 if (readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL)
Simon Glassc54c0a42015-10-17 19:41:22 -060099 return -EAGAIN;
100
101 writel(c, &regs->tx_rx_fifo);
102
103 return 0;
104}
105
Michal Simekb729ed02018-06-14 11:19:57 +0200106static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
Michal Simek194846f2012-09-14 00:55:24 +0000107{
Michal Simek6bdf0a92018-06-14 10:32:27 +0200108 struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
Michal Simek59da82e2016-07-14 14:40:03 +0200109 unsigned long clock;
Michal Simek194846f2012-09-14 00:55:24 +0000110
Michal Simek59da82e2016-07-14 14:40:03 +0200111 int ret;
112 struct clk clk;
113
114 ret = clk_get_by_index(dev, 0, &clk);
115 if (ret < 0) {
116 dev_err(dev, "failed to get clock\n");
117 return ret;
118 }
119
120 clock = clk_get_rate(&clk);
121 if (IS_ERR_VALUE(clock)) {
122 dev_err(dev, "failed to get rate\n");
123 return clock;
124 }
125 debug("%s: CLK %ld\n", __func__, clock);
126
127 ret = clk_enable(&clk);
128 if (ret && ret != -ENOSYS) {
129 dev_err(dev, "failed to enable clock\n");
130 return ret;
131 }
Stefan Herbrechtsmeier781745b2017-01-17 16:27:30 +0100132
Michal Simek6bdf0a92018-06-14 10:32:27 +0200133 _uart_zynq_serial_setbrg(platdata->regs, clock, baudrate);
Michal Simek194846f2012-09-14 00:55:24 +0000134
Simon Glass42800ff2015-10-17 19:41:27 -0600135 return 0;
Michal Simek194846f2012-09-14 00:55:24 +0000136}
137
Simon Glass42800ff2015-10-17 19:41:27 -0600138static int zynq_serial_probe(struct udevice *dev)
Michal Simek194846f2012-09-14 00:55:24 +0000139{
Michal Simek6bdf0a92018-06-14 10:32:27 +0200140 struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
Michal Simek895a7862020-03-24 11:31:42 +0100141 struct uart_zynq *regs = platdata->regs;
142 u32 val;
Simon Glass42800ff2015-10-17 19:41:27 -0600143
Michal Simek895a7862020-03-24 11:31:42 +0100144 /* No need to reinitialize the UART if TX already enabled */
145 val = readl(&regs->control);
146 if (val & ZYNQ_UART_CR_TX_EN)
Michal Simeka6730252018-06-14 10:41:35 +0200147 return 0;
148
Michal Simek6bdf0a92018-06-14 10:32:27 +0200149 _uart_zynq_serial_init(platdata->regs);
Simon Glass42800ff2015-10-17 19:41:27 -0600150
151 return 0;
Michal Simek194846f2012-09-14 00:55:24 +0000152}
153
Simon Glass42800ff2015-10-17 19:41:27 -0600154static int zynq_serial_getc(struct udevice *dev)
Michal Simek194846f2012-09-14 00:55:24 +0000155{
Michal Simek6bdf0a92018-06-14 10:32:27 +0200156 struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
157 struct uart_zynq *regs = platdata->regs;
Michal Simek194846f2012-09-14 00:55:24 +0000158
Simon Glass42800ff2015-10-17 19:41:27 -0600159 if (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY)
160 return -EAGAIN;
Michal Simek194846f2012-09-14 00:55:24 +0000161
Michal Simek194846f2012-09-14 00:55:24 +0000162 return readl(&regs->tx_rx_fifo);
163}
164
Simon Glass42800ff2015-10-17 19:41:27 -0600165static int zynq_serial_putc(struct udevice *dev, const char ch)
Michal Simekc9416b92014-02-24 11:16:33 +0100166{
Michal Simek6bdf0a92018-06-14 10:32:27 +0200167 struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
Michal Simekc9416b92014-02-24 11:16:33 +0100168
Michal Simek6bdf0a92018-06-14 10:32:27 +0200169 return _uart_zynq_serial_putc(platdata->regs, ch);
Michal Simekc9416b92014-02-24 11:16:33 +0100170}
Tom Rini51d81022012-10-08 14:46:23 -0700171
Simon Glass42800ff2015-10-17 19:41:27 -0600172static int zynq_serial_pending(struct udevice *dev, bool input)
Tom Rini51d81022012-10-08 14:46:23 -0700173{
Michal Simek6bdf0a92018-06-14 10:32:27 +0200174 struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
175 struct uart_zynq *regs = platdata->regs;
Simon Glass42800ff2015-10-17 19:41:27 -0600176
177 if (input)
178 return !(readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY);
179 else
180 return !!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXACTIVE);
Tom Rini51d81022012-10-08 14:46:23 -0700181}
Simon Glassc54c0a42015-10-17 19:41:22 -0600182
Simon Glass42800ff2015-10-17 19:41:27 -0600183static int zynq_serial_ofdata_to_platdata(struct udevice *dev)
184{
Michal Simek6bdf0a92018-06-14 10:32:27 +0200185 struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
Simon Glass42800ff2015-10-17 19:41:27 -0600186
Michal Simek6bdf0a92018-06-14 10:32:27 +0200187 platdata->regs = (struct uart_zynq *)dev_read_addr(dev);
188 if (IS_ERR(platdata->regs))
189 return PTR_ERR(platdata->regs);
Simon Glass42800ff2015-10-17 19:41:27 -0600190
191 return 0;
192}
193
194static const struct dm_serial_ops zynq_serial_ops = {
195 .putc = zynq_serial_putc,
196 .pending = zynq_serial_pending,
197 .getc = zynq_serial_getc,
198 .setbrg = zynq_serial_setbrg,
199};
200
201static const struct udevice_id zynq_serial_ids[] = {
202 { .compatible = "xlnx,xuartps" },
203 { .compatible = "cdns,uart-r1p8" },
Michal Simeka2533182016-01-14 11:45:52 +0100204 { .compatible = "cdns,uart-r1p12" },
Simon Glass42800ff2015-10-17 19:41:27 -0600205 { }
206};
207
Michal Simek6bf87da2015-12-01 14:29:34 +0100208U_BOOT_DRIVER(serial_zynq) = {
Simon Glass42800ff2015-10-17 19:41:27 -0600209 .name = "serial_zynq",
210 .id = UCLASS_SERIAL,
211 .of_match = zynq_serial_ids,
212 .ofdata_to_platdata = zynq_serial_ofdata_to_platdata,
Michal Simek6bdf0a92018-06-14 10:32:27 +0200213 .platdata_auto_alloc_size = sizeof(struct zynq_uart_platdata),
Simon Glass42800ff2015-10-17 19:41:27 -0600214 .probe = zynq_serial_probe,
215 .ops = &zynq_serial_ops,
Simon Glass42800ff2015-10-17 19:41:27 -0600216};
217
Simon Glassc54c0a42015-10-17 19:41:22 -0600218#ifdef CONFIG_DEBUG_UART_ZYNQ
Michal Simek80dc9992016-01-05 12:49:21 +0100219static inline void _debug_uart_init(void)
Simon Glassc54c0a42015-10-17 19:41:22 -0600220{
221 struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
222
223 _uart_zynq_serial_init(regs);
224 _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
225 CONFIG_BAUDRATE);
226}
227
228static inline void _debug_uart_putc(int ch)
229{
230 struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
231
232 while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
233 WATCHDOG_RESET();
234}
235
236DEBUG_UART_FUNCS
237
238#endif