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wdenk04a85b32004-04-15 18:22:41 +00001/*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
26 * U-Boot port on NetTA4 board
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/*
33 * High Level Configuration Options
34 * (easy to change)
35 */
36
37#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
38#define CONFIG_NETTA 1 /* ...on a NetTA board */
39
40#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
41#undef CONFIG_8xx_CONS_SMC2
42#undef CONFIG_8xx_CONS_NONE
43
44#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
45
46/* #define CONFIG_XIN 10000000 */
47#define CONFIG_XIN 50000000
48#define MPC8XX_HZ 120000000
49/* #define MPC8XX_HZ 100000000 */
50/* #define MPC8XX_HZ 50000000 */
51/* #define MPC8XX_HZ 80000000 */
52
53#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
54
55#if 0
56#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
57#else
58#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
59#endif
60
61#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
62
63#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
64
65#undef CONFIG_BOOTARGS
66#define CONFIG_BOOTCOMMAND \
67 "tftpboot; " \
wdenk79fa88f2004-06-07 23:46:25 +000068 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
69 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk04a85b32004-04-15 18:22:41 +000070 "bootm"
71
72#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
73#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
74
75#undef CONFIG_WATCHDOG /* watchdog disabled */
76#define CONFIG_HW_WATCHDOG
77
78#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
79
80#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
81
82#undef CONFIG_MAC_PARTITION
83#undef CONFIG_DOS_PARTITION
84
85#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
86
87#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
88#define FEC_ENET 1 /* eth.c needs it that way... */
89#undef CFG_DISCOVER_PHY /* do not discover phys */
90#define CONFIG_MII 1
91#define CONFIG_RMII 1 /* use RMII interface */
92
93#if defined(CONFIG_NETTA_ISDN)
94#define CONFIG_ETHER_ON_FEC1 1
95#define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */
96#define CONFIG_FEC1_PHY_NORXERR 1
97#undef CONFIG_ETHER_ON_FEC2
98#else
99#define CONFIG_ETHER_ON_FEC1 1
100#define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */
101#define CONFIG_FEC1_PHY_NORXERR 1
102#define CONFIG_ETHER_ON_FEC2 1
103#define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */
104#define CONFIG_FEC2_PHY_NORXERR 1
105#endif
106
107#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
108
109/* POST support */
110#define CONFIG_POST (CFG_POST_MEMORY | \
wdenk79fa88f2004-06-07 23:46:25 +0000111 CFG_POST_CODEC | \
wdenk04a85b32004-04-15 18:22:41 +0000112 CFG_POST_DSP )
113
114#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
wdenk79fa88f2004-06-07 23:46:25 +0000115 CFG_CMD_CDP | \
wdenk04a85b32004-04-15 18:22:41 +0000116 CFG_CMD_DHCP | \
wdenk04a85b32004-04-15 18:22:41 +0000117 CFG_CMD_DIAG | \
wdenk79fa88f2004-06-07 23:46:25 +0000118 CFG_CMD_FAT | \
119 CFG_CMD_IDE | \
120 CFG_CMD_JFFS2 | \
121 CFG_CMD_MII | \
122 CFG_CMD_NAND | \
wdenkc26e4542004-04-18 10:13:26 +0000123 CFG_CMD_NFS | \
wdenk79fa88f2004-06-07 23:46:25 +0000124 CFG_CMD_PCMCIA | \
125 CFG_CMD_PING | \
126 0)
wdenk04a85b32004-04-15 18:22:41 +0000127
128#define CONFIG_BOARD_EARLY_INIT_F 1
129#define CONFIG_MISC_INIT_R
130
131/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
132#include <cmd_confdefs.h>
133
134/*
135 * Miscellaneous configurable options
136 */
137#define CFG_LONGHELP /* undef to save memory */
138#define CFG_PROMPT "=> " /* Monitor Command Prompt */
139
140#define CFG_HUSH_PARSER 1
141#define CFG_PROMPT_HUSH_PS2 "> "
142
143#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
144#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
145#else
146#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
147#endif
148#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
149#define CFG_MAXARGS 16 /* max number of command args */
150#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
151
152#define CFG_MEMTEST_START 0x0300000 /* memtest works on */
153#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
154
155#define CFG_LOAD_ADDR 0x100000 /* default load address */
156
157#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
158
159#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
160
161/*
162 * Low Level Configuration Settings
163 * (address mappings, register initial values, etc.)
164 * You should know what you are doing if you make changes here.
165 */
166/*-----------------------------------------------------------------------
167 * Internal Memory Mapped Register
168 */
169#define CFG_IMMR 0xFF000000
170
171/*-----------------------------------------------------------------------
172 * Definitions for initial stack pointer and data area (in DPRAM)
173 */
174#define CFG_INIT_RAM_ADDR CFG_IMMR
175#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
176#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
177#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
178#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
179
180/*-----------------------------------------------------------------------
181 * Start addresses for the final memory configuration
182 * (Set up by the startup code)
183 * Please note that CFG_SDRAM_BASE _must_ start at 0
184 */
185#define CFG_SDRAM_BASE 0x00000000
186#define CFG_FLASH_BASE 0x40000000
187#if defined(DEBUG)
188#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
189#else
190#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
191#endif
192#define CFG_MONITOR_BASE CFG_FLASH_BASE
193#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
194
195/*
196 * For booting Linux, the board info and command line data
197 * have to be in the first 8 MB of memory, since this is
198 * the maximum mapped by the Linux kernel during initialization.
199 */
200#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
201
202/*-----------------------------------------------------------------------
203 * FLASH organization
204 */
205#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
206#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
207
208#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
209#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
210
211#define CFG_ENV_IS_IN_FLASH 1
212#define CFG_ENV_SECT_SIZE 0x10000
213
214#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000)
215#define CFG_ENV_OFFSET 0
216#define CFG_ENV_SIZE 0x4000
217
218#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000)
219#define CFG_ENV_OFFSET_REDUND 0
220#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
221
222/*-----------------------------------------------------------------------
223 * Cache Configuration
224 */
225#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
226#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
227#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
228#endif
229
230/*-----------------------------------------------------------------------
231 * SYPCR - System Protection Control 11-9
232 * SYPCR can only be written once after reset!
233 *-----------------------------------------------------------------------
234 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
235 */
236#if defined(CONFIG_WATCHDOG)
237#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
238 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
239#else
240#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
241#endif
242
243/*-----------------------------------------------------------------------
244 * SIUMCR - SIU Module Configuration 11-6
245 *-----------------------------------------------------------------------
246 * PCMCIA config., multi-function pin tri-state
247 */
248#ifndef CONFIG_CAN_DRIVER
249#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
250#else /* we must activate GPL5 in the SIUMCR for CAN */
251#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
252#endif /* CONFIG_CAN_DRIVER */
253
254/*-----------------------------------------------------------------------
255 * TBSCR - Time Base Status and Control 11-26
256 *-----------------------------------------------------------------------
257 * Clear Reference Interrupt Status, Timebase freezing enabled
258 */
259#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
260
261/*-----------------------------------------------------------------------
262 * RTCSC - Real-Time Clock Status and Control Register 11-27
263 *-----------------------------------------------------------------------
264 */
265#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
266
267/*-----------------------------------------------------------------------
268 * PISCR - Periodic Interrupt Status and Control 11-31
269 *-----------------------------------------------------------------------
270 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
271 */
272#define CFG_PISCR (PISCR_PS | PISCR_PITF)
273
274/*-----------------------------------------------------------------------
275 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
276 *-----------------------------------------------------------------------
277 * Reset PLL lock status sticky bit, timer expired status bit and timer
278 * interrupt status bit
279 *
280 */
281
282#if CONFIG_XIN == 10000000
283
284#if MPC8XX_HZ == 120000000
285#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
286 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
287 PLPRCR_TEXPS)
288#elif MPC8XX_HZ == 100000000
289#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
290 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
291 PLPRCR_TEXPS)
292#elif MPC8XX_HZ == 50000000
293#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
294 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
295 PLPRCR_TEXPS)
296#elif MPC8XX_HZ == 25000000
297#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
298 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
299 PLPRCR_TEXPS)
300#elif MPC8XX_HZ == 40000000
301#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
302 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
303 PLPRCR_TEXPS)
304#elif MPC8XX_HZ == 75000000
305#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
306 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
307 PLPRCR_TEXPS)
308#else
309#error unsupported CPU freq for XIN = 10MHz
310#endif
311
312#elif CONFIG_XIN == 50000000
313
314#if MPC8XX_HZ == 120000000
315#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
316 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
317 PLPRCR_TEXPS)
318#elif MPC8XX_HZ == 100000000
319#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
320 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
321 PLPRCR_TEXPS)
322#elif MPC8XX_HZ == 80000000
323#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
324 (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
325 PLPRCR_TEXPS)
326#elif MPC8XX_HZ == 50000000
327#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
328 (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
329 PLPRCR_TEXPS)
330#else
331#error unsupported CPU freq for XIN = 50MHz
332#endif
333
334#else
335
336#error unsupported XIN freq
337#endif
338
339
340/*
341 *-----------------------------------------------------------------------
342 * SCCR - System Clock and reset Control Register 15-27
343 *-----------------------------------------------------------------------
344 * Set clock output, timebase and RTC source and divider,
345 * power management and some other internal clocks
wdenk79fa88f2004-06-07 23:46:25 +0000346 *
347 * Note: When TBS == 0 the timebase is independent of current cpu clock.
wdenk04a85b32004-04-15 18:22:41 +0000348 */
349
350#define SCCR_MASK SCCR_EBDF11
351#if MPC8XX_HZ > 66666666
wdenk79fa88f2004-06-07 23:46:25 +0000352#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
wdenk04a85b32004-04-15 18:22:41 +0000353 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenk79fa88f2004-06-07 23:46:25 +0000354 SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \
wdenk04a85b32004-04-15 18:22:41 +0000355 SCCR_DFALCD00 | SCCR_EBDF01)
356#else
wdenk79fa88f2004-06-07 23:46:25 +0000357#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
wdenk04a85b32004-04-15 18:22:41 +0000358 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenk79fa88f2004-06-07 23:46:25 +0000359 SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \
wdenk04a85b32004-04-15 18:22:41 +0000360 SCCR_DFALCD00)
361#endif
362
363/*-----------------------------------------------------------------------
364 *
365 *-----------------------------------------------------------------------
366 *
367 */
368/*#define CFG_DER 0x2002000F*/
369#define CFG_DER 0
370
371/*
372 * Init Memory Controller:
373 *
374 * BR0/1 and OR0/1 (FLASH)
375 */
376
377#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
378
379/* used to re-map FLASH both when starting from SRAM or FLASH:
380 * restrict access enough to keep SRAM working (if any)
381 * but not too much to meddle with FLASH accesses
382 */
383#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
384#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
385
386/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
387#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
388
389#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
390#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
391#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
392
393/*
394 * BR3 and OR3 (SDRAM)
395 *
396 */
397#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
398#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
399
400/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
401#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
402
403#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
404#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
405
406/*
407 * Memory Periodic Timer Prescaler
408 */
409
410/*
411 * Memory Periodic Timer Prescaler
412 *
413 * The Divider for PTA (refresh timer) configuration is based on an
414 * example SDRAM configuration (64 MBit, one bank). The adjustment to
415 * the number of chip selects (NCS) and the actually needed refresh
416 * rate is done by setting MPTPR.
417 *
418 * PTA is calculated from
419 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
420 *
421 * gclk CPU clock (not bus clock!)
422 * Trefresh Refresh cycle * 4 (four word bursts used)
423 *
424 * 4096 Rows from SDRAM example configuration
425 * 1000 factor s -> ms
426 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
427 * 4 Number of refresh cycles per period
428 * 64 Refresh cycle in ms per number of rows
429 * --------------------------------------------
430 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
431 *
432 * 50 MHz => 50.000.000 / Divider = 98
433 * 66 Mhz => 66.000.000 / Divider = 129
434 * 80 Mhz => 80.000.000 / Divider = 156
435 */
436
437#if MPC8XX_HZ == 120000000
438#define CFG_MAMR_PTA 234
439#elif MPC8XX_HZ == 100000000
440#define CFG_MAMR_PTA 195
441#elif MPC8XX_HZ == 80000000
442#define CFG_MAMR_PTA 156
443#elif MPC8XX_HZ == 50000000
444#define CFG_MAMR_PTA 98
445#else
446#error Unknown frequency
447#endif
448
449
450/*
451 * For 16 MBit, refresh rates could be 31.3 us
452 * (= 64 ms / 2K = 125 / quad bursts).
453 * For a simpler initialization, 15.6 us is used instead.
454 *
455 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
456 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
457 */
458#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
459#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
460
461/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
462#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
463#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
464
465/*
466 * MAMR settings for SDRAM
467 */
468
469/* 8 column SDRAM */
470#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
471 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
472 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
473
474/* 9 column SDRAM */
475#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
476 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
477 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
478
479/*
480 * Internal Definitions
481 *
482 * Boot Flags
483 */
484#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
485#define BOOTFLAG_WARM 0x02 /* Software reboot */
486
487#define CONFIG_ARTOS /* include ARTOS support */
488
489#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
490
491/***********************************************************************************************************
492
493 Pin definitions:
494
495 +------+----------------+--------+------------------------------------------------------------
496 | # | Name | Type | Comment
497 +------+----------------+--------+------------------------------------------------------------
498 | PA3 | OK_ETH_3V | Input | CISCO Ethernet power OK
499 | | | | (NetRoute: FEC1, TA: FEC2) (0=power OK)
500 | PA6 | P_VCCD1 | Output | TPS2211A PCMCIA
501 | PA7 | DCL1_3V | Periph | IDL1 PCM clock
502 | PA8 | DSP_DR1 | Periph | IDL1 PCM Data Rx
503 | PA9 | L1TXDA | Periph | IDL1 PCM Data Tx
504 | PA10 | P_VCCD0 | Output | TPS2211A PCMCIA
505 | PA12 | P_SHDN | Output | TPS2211A PCMCIA
506 | PA13 | ETH_LOOP | Output | CISCO Loopback remote power
507 | | | | (NetRoute: FEC1, TA: FEC2) (1=NORMAL)
508 | PA14 | P_VPPD0 | Output | TPS2211A PCMCIA
509 | PA15 | P_VPPD1 | Output | TPS2211A PCMCIA
510 | PB14 | SPIEN_FXO | Output | SPI CS for FXO daughter-board
511 | PB15 | SPIEN_S1 | Output | SPI CS for S-interface 1 (NetRoute only)
512 | PB16 | DREQ1 | Output | D channel request for S-interface chip 1.
513 | PB17 | L1ST3 | Periph | IDL1 timeslot enable signal for PPC
514 | PB18 | L1ST2 | Periph | IDL1 timeslot enable signal for PPC
515 | PB19 | SPIEN_S2 | Output | SPI CS for S-interface 2 (NetRoute only)
516 | PB20 | SPIEN_SEEPROM | Output | SPI CS for serial eeprom
517 | PB21 | LEDIO | Output | Led mode indication for PHY
518 | PB22 | UART_CTS | Input | UART CTS
519 | PB23 | UART_RTS | Output | UART RTS
520 | PB24 | UART_RX | Periph | UART Data Rx
521 | PB25 | UART_TX | Periph | UART Data Tx
522 | PB26 | RMII-MDC | Periph | Free for future use (MII mgt clock)
523 | PB27 | RMII-MDIO | Periph | Free for future use (MII mgt data)
524 | PB28 | SPI_RXD_3V | Input | SPI Data Rx
525 | PB29 | SPI_TXD | Output | SPI Data Tx
526 | PB30 | SPI_CLK | Output | SPI Clock
527 | PB31 | RMII1-REFCLK | Periph | RMII reference clock for FEC1
528 | PC4 | PHY1_LINK | Input | PHY link state FEC1 (interrupt)
529 | PC5 | PHY2_LINK | Input | PHY link state FEC2 (interrupt)
530 | PC6 | RMII1-MDINT | Input | PHY prog interrupt FEC1 (interrupt)
531 | PC7 | RMII2-MDINT | Input | PHY prog interrupt FEC1 (interrupt)
532 | PC8 | P_OC | Input | TPS2211A PCMCIA overcurrent (interrupt) (1=OK)
533 | PC9 | COM_HOOK1 | Input | Codec interrupt chip #1 (interrupt)
534 | PC10 | COM_HOOK2 | Input | Codec interrupt chip #2 (interrupt)
535 | PC11 | COM_HOOK4 | Input | Codec interrupt chip #4 (interrupt)
536 | PC12 | COM_HOOK3 | Input | Codec interrupt chip #3 (interrupt)
537 | PC13 | F_RY_BY | Input | NAND ready signal (interrupt)
538 | PC14 | FAN_OK | Input | Fan status signal (interrupt) (1=OK)
539 | PC15 | PC15_DIRECT0 | Periph | PCMCIA DMA request.
540 | PD3 | F_ALE | Output | NAND
541 | PD4 | F_CLE | Output | NAND
542 | PD5 | F_CE | Output | NAND
543 | PD6 | DSP_INT | Output | DSP debug interrupt
544 | PD7 | DSP_RESET | Output | DSP reset
545 | PD8 | RMII_MDC | Periph | MII mgt clock
546 | PD9 | SPIEN_C1 | Output | SPI CS for codec #1
547 | PD10 | SPIEN_C2 | Output | SPI CS for codec #2
548 | PD11 | SPIEN_C3 | Output | SPI CS for codec #3
549 | PD12 | FSC2 | Periph | IDL2 frame sync
550 | PD13 | DGRANT2 | Input | D channel grant from S #2
551 | PD14 | SPIEN_C4 | Output | SPI CS for codec #4
552 | PD15 | TP700 | Output | Testpoint for software debugging
553 | PE14 | RMII2-TXD0 | Periph | FEC2 transmit data
554 | PE15 | RMII2-TXD1 | Periph | FEC2 transmit data
555 | PE16 | RMII2-REFCLK | Periph | TA: RMII ref clock for
556 | | DCL2 | Periph | NetRoute: PCM clock #2
557 | PE17 | TP703 | Output | Testpoint for software debugging
558 | PE18 | DGRANT1 | Input | D channel grant from S #1
559 | PE19 | RMII2-TXEN | Periph | TA: FEC2 tx enable
560 | | PCM2OUT | Periph | NetRoute: Tx data for IDL2
561 | PE20 | FSC1 | Periph | IDL1 frame sync
562 | PE21 | RMII2-RXD0 | Periph | FEC2 receive data
563 | PE22 | RMII2-RXD1 | Periph | FEC2 receive data
564 | PE23 | L1ST1 | Periph | IDL1 timeslot enable signal for PPC
565 | PE24 | U-N1 | Output | Select user/network for S #1 (0=user)
566 | PE25 | U-N2 | Output | Select user/network for S #2 (0=user)
567 | PE26 | RMII2-RXDV | Periph | FEC2 valid
568 | PE27 | DREQ2 | Output | D channel request for S #2.
569 | PE28 | FPGA_DONE | Input | FPGA done signal
570 | PE29 | FPGA_INIT | Output | FPGA init signal
571 | PE30 | UDOUT2_3V | Input | IDL2 PCM input
572 | PE31 | | | Free
573 +------+----------------+--------+---------------------------------------------------
574
575 Chip selects:
576
577 +------+----------------+------------------------------------------------------------
578 | # | Name | Comment
579 +------+----------------+------------------------------------------------------------
580 | CS0 | CS0 | Boot flash
581 | CS1 | CS_FLASH | NAND flash
582 | CS2 | CS_DSP | DSP
583 | CS3 | DCS_DRAM | DRAM
584 | CS4 | CS_ER1 | External output register
585 +------+----------------+------------------------------------------------------------
586
587 Interrupts:
588
589 +------+----------------+------------------------------------------------------------
590 | # | Name | Comment
591 +------+----------------+------------------------------------------------------------
592 | IRQ1 | UINTER_3V | S interupt chips interrupt (common)
593 | IRQ3 | IRQ_DSP | DSP interrupt
594 | IRQ4 | IRQ_DSP1 | Extra DSP interrupt
595 +------+----------------+------------------------------------------------------------
596
597*************************************************************************************************/
598
599#define DSP_SIZE 0x00010000 /* 64K */
600#define NAND_SIZE 0x00010000 /* 64K */
601#define ER_SIZE 0x00010000 /* 64K */
602#define DUMMY_SIZE 0x00010000 /* 64K */
603
604#define DSP_BASE 0xF1000000
605#define NAND_BASE 0xF1010000
606#define ER_BASE 0xF1020000
607#define DUMMY_BASE 0xF1FF0000
608
609/****************************************************************/
610
611/* NAND */
612#define CFG_NAND_BASE NAND_BASE
wdenk79fa88f2004-06-07 23:46:25 +0000613#define CONFIG_MTD_NAND_VERIFY_WRITE
614#define CONFIG_MTD_NAND_UNSAFE
wdenk04a85b32004-04-15 18:22:41 +0000615
616#define CFG_MAX_NAND_DEVICE 1
wdenk79fa88f2004-06-07 23:46:25 +0000617/* #define NAND_NO_RB */
wdenk04a85b32004-04-15 18:22:41 +0000618
619#define SECTORSIZE 512
620#define ADDR_COLUMN 1
621#define ADDR_PAGE 2
622#define ADDR_COLUMN_PAGE 3
623#define NAND_ChipID_UNKNOWN 0x00
624#define NAND_MAX_FLOORS 1
625#define NAND_MAX_CHIPS 1
626
627/* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */
628#define NAND_DISABLE_CE(nand) \
629 do { \
630 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 5)); \
631 } while(0)
632
633#define NAND_ENABLE_CE(nand) \
634 do { \
635 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 5)); \
636 } while(0)
637
638#define NAND_CTL_CLRALE(nandptr) \
639 do { \
640 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 3)); \
641 } while(0)
642
643#define NAND_CTL_SETALE(nandptr) \
644 do { \
645 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 3)); \
646 } while(0)
647
648#define NAND_CTL_CLRCLE(nandptr) \
649 do { \
650 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 4)); \
651 } while(0)
652
653#define NAND_CTL_SETCLE(nandptr) \
654 do { \
655 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 4)); \
656 } while(0)
657
658#ifndef NAND_NO_RB
659#define NAND_WAIT_READY(nand) \
660 do { \
661 while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 13))) == 0) { \
662 WATCHDOG_RESET(); \
663 } \
664 } while (0)
665#else
666#define NAND_WAIT_READY(nand) udelay(12)
667#endif
668
669#define WRITE_NAND_COMMAND(d, adr) \
670 do { \
671 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
672 } while(0)
673
674#define WRITE_NAND_ADDRESS(d, adr) \
675 do { \
676 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
677 } while(0)
678
679#define WRITE_NAND(d, adr) \
680 do { \
681 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
682 } while(0)
683
684#define READ_NAND(adr) \
685 ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
686
wdenk79fa88f2004-06-07 23:46:25 +0000687#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
688#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */
689#define CONFIG_JFFS2_NAND_OFF (2 * 1024 * 1024) /* start of jffs2 partition */
690#define CONFIG_JFFS2_NAND_SIZE (1*1024*1024) /* size of jffs2 partition */
691#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
692
693/*****************************************************************************/
694
695#define CFG_DIRECT_FLASH_TFTP
696#define CFG_DIRECT_NAND_TFTP
697
wdenk04a85b32004-04-15 18:22:41 +0000698/*****************************************************************************/
699
700#if 1
701/*-----------------------------------------------------------------------
702 * PCMCIA stuff
703 *-----------------------------------------------------------------------
704 */
705
706#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
707#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
708#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
709#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
710#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
711#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
712#define CFG_PCMCIA_IO_ADDR (0xEC000000)
713#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
714
715/*-----------------------------------------------------------------------
716 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
717 *-----------------------------------------------------------------------
718 */
719
720#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
721
722#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
723#undef CONFIG_IDE_LED /* LED for ide not supported */
724#undef CONFIG_IDE_RESET /* reset for ide not supported */
725
726#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
727#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
728
729#define CFG_ATA_IDE0_OFFSET 0x0000
730
731#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
732
733/* Offset for data I/O */
734#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
735
736/* Offset for normal register accesses */
737#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
738
739/* Offset for alternate registers */
740#define CFG_ATA_ALT_OFFSET 0x0100
741
742#define CONFIG_MAC_PARTITION
743#define CONFIG_DOS_PARTITION
744#endif
745
746/*************************************************************************************************/
747
748#define CONFIG_CDP_DEVICE_ID 20
749#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta */
750#define CONFIG_CDP_PORT_ID "eth%d"
751#define CONFIG_CDP_CAPABILITIES 0x00000010
752#define CONFIG_CDP_VERSION "u-boot 1.0" " " __DATE__ " " __TIME__
753#define CONFIG_CDP_PLATFORM "Intracom NetTA"
754#define CONFIG_CDP_TRIGGER 0x20020001
755#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */
756#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone? */
757
758/*************************************************************************************************/
759
760#define CONFIG_AUTO_COMPLETE 1
761
762/*************************************************************************************************/
763
wdenkc26e4542004-04-18 10:13:26 +0000764#define CONFIG_CRC32_VERIFY 1
765
766/*************************************************************************************************/
767
768#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
769
770/*************************************************************************************************/
771
wdenk04a85b32004-04-15 18:22:41 +0000772#endif /* __CONFIG_H */