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gerrit.cesnet.cz / github / trini / u-boot / 8915a40da4298ebe69052e3538cd33f917a85351 / . / arch / arm / mach-k3 / arm64-mmu.c
blob: b1d1d6e494fce076d84093ad851a17d7303ccabf [file] [log] [blame]
Lokesh Vutlae0918322018-08-27 15:57:13 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * K3: ARM64 MMU setup
4 *
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
Michal Simek274ccb52019-01-17 08:22:43 +0100[diff] [blame]7 * (This file is derived from arch/arm/mach-zynqmp/cpu.c)
Lokesh Vutlae0918322018-08-27 15:57:13 +0530[diff] [blame]8 *
9 */
10
11#include <common.h>
12#include <asm/system.h>
13#include <asm/armv8/mmu.h>
14
Suman Anna5bc22e32019-06-13 10:29:48 +0530[diff] [blame]15#ifdef CONFIG_SOC_K3_AM6
Lokesh Vutlae0918322018-08-27 15:57:13 +0530[diff] [blame]16/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
Suman Anna60bdc6b2019-09-04 16:01:49 +0530[diff] [blame]17#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
Lokesh Vutlae0918322018-08-27 15:57:13 +0530[diff] [blame]18
19/* ToDo: Add 64bit IO */
20struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
21 {
22 .virt = 0x0UL,
23 .phys = 0x0UL,
24 .size = 0x80000000UL,
25 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
26 PTE_BLOCK_NON_SHARE |
27 PTE_BLOCK_PXN | PTE_BLOCK_UXN
28 }, {
29 .virt = 0x80000000UL,
30 .phys = 0x80000000UL,
Suman Anna60bdc6b2019-09-04 16:01:49 +0530[diff] [blame]31 .size = 0x20000000UL,
32 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
33 PTE_BLOCK_INNER_SHARE
34 }, {
35 .virt = 0xa0000000UL,
36 .phys = 0xa0000000UL,
37 .size = 0x02100000UL,
38 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
39 PTE_BLOCK_INNER_SHARE
40 }, {
41 .virt = 0xa2100000UL,
42 .phys = 0xa2100000UL,
43 .size = 0x5df00000UL,
Lokesh Vutlae0918322018-08-27 15:57:13 +0530[diff] [blame]44 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
45 PTE_BLOCK_INNER_SHARE
46 }, {
47 .virt = 0x880000000UL,
48 .phys = 0x880000000UL,
49 .size = 0x80000000UL,
50 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
51 PTE_BLOCK_INNER_SHARE
52 }, {
Vignesh Raghavendra8915a402020-02-04 11:09:49 +0530[diff] [blame^]53 .virt = 0x500000000UL,
54 .phys = 0x500000000UL,
55 .size = 0x400000000UL,
56 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
57 PTE_BLOCK_NON_SHARE |
58 PTE_BLOCK_PXN | PTE_BLOCK_UXN
59 }, {
Lokesh Vutlae0918322018-08-27 15:57:13 +0530[diff] [blame]60 /* List terminator */
61 0,
62 }
63};
64
65struct mm_region *mem_map = am654_mem_map;
Suman Anna5bc22e32019-06-13 10:29:48 +0530[diff] [blame]66#endif /* CONFIG_SOC_K3_AM6 */
67
68#ifdef CONFIG_SOC_K3_J721E
69/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
70#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
71
72/* ToDo: Add 64bit IO */
73struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
74 {
75 .virt = 0x0UL,
76 .phys = 0x0UL,
77 .size = 0x80000000UL,
78 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
79 PTE_BLOCK_NON_SHARE |
80 PTE_BLOCK_PXN | PTE_BLOCK_UXN
81 }, {
82 .virt = 0x80000000UL,
83 .phys = 0x80000000UL,
84 .size = 0x20000000UL,
85 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
86 PTE_BLOCK_INNER_SHARE
87 }, {
88 .virt = 0xa0000000UL,
89 .phys = 0xa0000000UL,
Kedar Chitnis8bdd83e2019-09-04 16:01:50 +0530[diff] [blame]90 .size = 0x1bc00000UL,
Suman Anna5bc22e32019-06-13 10:29:48 +0530[diff] [blame]91 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
92 PTE_BLOCK_NON_SHARE
93 }, {
Kedar Chitnis8bdd83e2019-09-04 16:01:50 +0530[diff] [blame]94 .virt = 0xbbc00000UL,
95 .phys = 0xbbc00000UL,
96 .size = 0x44400000UL,
Suman Anna5bc22e32019-06-13 10:29:48 +0530[diff] [blame]97 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
98 PTE_BLOCK_INNER_SHARE
99 }, {
100 .virt = 0x880000000UL,
101 .phys = 0x880000000UL,
102 .size = 0x80000000UL,
103 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
104 PTE_BLOCK_INNER_SHARE
105 }, {
106 .virt = 0x500000000UL,
107 .phys = 0x500000000UL,
108 .size = 0x400000000UL,
109 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
110 PTE_BLOCK_NON_SHARE |
111 PTE_BLOCK_PXN | PTE_BLOCK_UXN
112 }, {
113 /* List terminator */
114 0,
115 }
116};
117
118struct mm_region *mem_map = j721e_mem_map;
119#endif /* CONFIG_SOC_K3_J721E */