blob: 85c0e612b2783e266f59da0b1c422b15425b1117 [file] [log] [blame]
Matthias Fuchs1a3ac862008-01-17 10:53:08 +01001/*
2 * (C) Copyright 2008
3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
4 *
5 * based on the Sequoia board configuration by
6 * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 **********************************************************************
26 * DU440.h - configuration for esd's DU440 board (Power PC440EPx)
27 **********************************************************************
28 */
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/*
33 * High Level Configuration Options
34 */
35#define CONFIG_DU440 1 /* Board is esd DU440 */
36#define CONFIG_440EPX 1 /* Specific PPC440EPx */
37#define CONFIG_4xx 1 /* ... PPC4xx family */
38#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */
39
40#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
41#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
42#define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */
43
44/*
45 * Base addresses -- Note these are effective addresses where the
46 * actual resources get mapped (not physical addresses)
47 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
49#define CONFIG_SYS_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010050
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
52#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
53#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
54#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
55#define CONFIG_SYS_NAND0_ADDR 0xd0000000 /* NAND Flash */
56#define CONFIG_SYS_NAND1_ADDR 0xd0100000 /* NAND Flash */
57#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
58#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
59#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
60#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
61#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
62#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
63#define CONFIG_SYS_PCI_IOBASE 0xe8000000
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010064
65
66/* Don't change either of these */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010068
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_USB2D0_BASE 0xe0000100
70#define CONFIG_SYS_USB_DEVICE 0xe0000000
71#define CONFIG_SYS_USB_HOST 0xe0000400
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010072
73/*
74 * Initial RAM & stack pointer
75 */
76/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_INIT_RAM_OCM 1 /* OCM as init ram */
78#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010079
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_INIT_RAM_END (4 << 10)
81#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
82#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
83#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010084
85/*
86 * Serial Port
87 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#undef CONFIG_SYS_EXT_SERIAL_CLOCK
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010089#define CONFIG_BAUDRATE 115200
90#define CONFIG_SERIAL_MULTI 1
91#undef CONFIG_UART1_CONSOLE
92
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_BAUDRATE_TABLE \
Matthias Fuchs1a3ac862008-01-17 10:53:08 +010094 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
95
96/*
97 * Video Port
98 */
99#define CONFIG_VIDEO
100#define CONFIG_VIDEO_SMI_LYNXEM
101#define CONFIG_CFB_CONSOLE
102#define CONFIG_VIDEO_LOGO
103#define CONFIG_VGA_AS_SINGLE_DEVICE
104#define CONFIG_SPLASH_SCREEN
105#define CONFIG_SPLASH_SCREEN_ALIGN
106#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img */
108#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */
109#define CONFIG_SYS_CONSOLE_IS_IN_ENV
110#define CONFIG_SYS_ISA_IO CONFIG_SYS_PCI_IOBASE
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100111
112/*
113 * Environment
114 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200115#define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100116
117/*
118 * FLASH related
119 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200121#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
126#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
129#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100132/* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_FLASH_EMPTY_INFO
136#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100137
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200138#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200139#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200141#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100142
143/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200144#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
145#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100146#endif
147
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200148#ifdef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200149#define CONFIG_ENV_OFFSET 0 /* environment starts at */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100150 /* the beginning of the EEPROM */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200151#define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100152#endif
153
154/*
155 * DDR SDRAM
156 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100158#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
Stefan Roese02e38922008-03-31 12:20:48 +0200160 /* 440EPx errata CHIP 11 */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100161#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100162#define CONFIG_DDR_ECC /* Use ECC when available */
163#define SPD_EEPROM_ADDRESS {0x50}
164#define CONFIG_PROG_SDRAM_TLB
165
166/*
167 * I2C
168 */
169#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
170#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
172#define CONFIG_SYS_I2C_SLAVE 0x7F
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100173#define CONFIG_I2C_CMD_TREE 1
174#define CONFIG_I2C_MULTI_BUS 1
175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_SPD_BUS_NUM 0
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100177#define IIC1_MCP3021_ADDR 0x4d
178#define IIC1_USB2507_ADDR 0x2c
179#ifdef CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_I2C_NOPROBES {{1, IIC1_USB2507_ADDR}}
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100181#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_I2C_MULTI_EEPROMS
183#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
184#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
185#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
186#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
187#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_EEPROM_WREN 1
190#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100191
192/*
193 * standard dtt sensor configuration - bottom bit will determine local or
194 * remote sensor of the TMP401
195 */
196#define CONFIG_DTT_SENSORS { 0, 1 }
197
198/*
199 * The PMC440 uses a TI TMP401 temperature sensor. This part
200 * is basically compatible to the ADM1021 that is supported
201 * by U-Boot.
202 *
203 * - i2c addr 0x4c
204 * - conversion rate 0x02 = 0.25 conversions/second
205 * - ALERT ouput disabled
206 * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
207 * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
208 */
209#define CONFIG_DTT_ADM1021
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100211
212/*
213 * RTC stuff
214 */
215#define CONFIG_RTC_DS1338
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100217
218#undef CONFIG_BOOTARGS
219
220#define CONFIG_EXTRA_ENV_SETTINGS \
221 "netdev=eth0\0" \
222 "ethrotate=no\0" \
223 "hostname=du440\0" \
224 "nfsargs=setenv bootargs root=/dev/nfs rw " \
225 "nfsroot=${serverip}:${rootpath}\0" \
226 "ramargs=setenv bootargs root=/dev/ram rw\0" \
227 "addip=setenv bootargs ${bootargs} " \
228 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
229 ":${hostname}:${netdev}:off panic=1\0" \
230 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
231 "flash_self=run ramargs addip addtty optargs;" \
232 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
233 "net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \
234 "bootm\0" \
235 "rootpath=/tftpboot/du440/target_root_du440\0" \
236 "img=/tftpboot/du440/uImage\0" \
237 "kernel_addr=FFC00000\0" \
238 "ramdisk_addr=FFE00000\0" \
239 "initrd_high=30000000\0" \
240 "load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \
241 "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
242 "cp.b 100000 FFFA0000 60000\0" \
243 ""
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100244
245#define CONFIG_PREBOOT /* enable preboot variable */
246
247#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
248
249#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100251
252#ifndef __ASSEMBLY__
253int du440_phy_addr(int devnum);
254#endif
255
Ben Warren96e21f82008-10-27 23:50:15 -0700256#define CONFIG_PPC4xx_EMAC
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100257#define CONFIG_IBM_EMAC4_V4 1
258#define CONFIG_MII 1 /* MII PHY management */
259#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */
260
261#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
Matthias Fuchs7c91f512008-03-30 18:01:15 +0200262#undef CONFIG_PHY_GIGE /* no GbE detection */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100263
264#define CONFIG_HAS_ETH0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_RX_ETH_BUFFER 128
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100266
267#define CONFIG_NET_MULTI 1
268#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
269#define CONFIG_PHY1_ADDR du440_phy_addr(1)
270
271/*
272 * USB
273 */
274#define CONFIG_USB_OHCI_NEW
275#define CONFIG_USB_STORAGE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_OHCI_BE_CONTROLLER
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100277
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
279#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
280#define CONFIG_SYS_USB_OHCI_SLOT_NAME "du440"
281#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100282
283/* Comment this out to enable USB 1.1 device */
284#define USB_2_0_DEVICE
285
286/* Partitions */
287#define CONFIG_MAC_PARTITION
288#define CONFIG_DOS_PARTITION
289#define CONFIG_ISO_PARTITION
290
291#include <config_cmd_default.h>
292
Matthias Fuchs7c91f512008-03-30 18:01:15 +0200293#define CONFIG_CMD_AUTOSCRIPT
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100294#define CONFIG_CMD_BSP
Matthias Fuchs7c91f512008-03-30 18:01:15 +0200295#define CONFIG_CMD_BMP
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100296#define CONFIG_CMD_DATE
297#define CONFIG_CMD_ASKENV
298#define CONFIG_CMD_DHCP
299#define CONFIG_CMD_DTT
300#define CONFIG_CMD_DIAG
301#define CONFIG_CMD_EEPROM
302#define CONFIG_CMD_ELF
303#define CONFIG_CMD_FAT
304#define CONFIG_CMD_I2C
305#define CONFIG_CMD_IRQ
306#define CONFIG_CMD_MII
307#define CONFIG_CMD_NAND
308#define CONFIG_CMD_NET
309#define CONFIG_CMD_NFS
310#define CONFIG_CMD_PCI
311#define CONFIG_CMD_PING
312#define CONFIG_CMD_USB
313#define CONFIG_CMD_REGINFO
314#define CONFIG_CMD_SDRAM
315
316#define CONFIG_SUPPORT_VFAT
317
318/*
319 * Miscellaneous configurable options
320 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_LONGHELP /* undef to save memory */
322#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100323#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100325#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100327#endif
328/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
330#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
331#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100332
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
334#define CONFIG_SYS_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100335
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
337#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100338
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100340
341#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
342#define CONFIG_LOOPW 1 /* enable loopw command */
343#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
344#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
345#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
346
Wolfgang Denkc37207d2008-07-16 16:38:59 +0200347#define CONFIG_AUTOBOOT_KEYED 1
348#define CONFIG_AUTOBOOT_PROMPT \
349 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100350#define CONFIG_AUTOBOOT_DELAY_STR "d"
351#define CONFIG_AUTOBOOT_STOP_STR " "
352
353/*
354 * PCI stuff
355 */
356#define CONFIG_PCI /* include pci support */
357#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
358#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100360
361/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_PCI_TARGET_INIT
363#define CONFIG_SYS_PCI_MASTER_INIT
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100364
365/*
366 * For booting Linux, the board info and command line data
367 * have to be in the first 8 MB of memory, since this is
368 * the maximum mapped by the Linux kernel during initialization.
369 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100371
372/*
373 * External Bus Controller (EBC) Setup
374 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100376
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_CPLD_BASE 0xC0000000
378#define CONFIG_SYS_CPLD_RANGE 0x00000010
379#define CONFIG_SYS_DUMEM_BASE 0xC0100000
380#define CONFIG_SYS_DUMEM_RANGE 0x00100000
381#define CONFIG_SYS_DUIO_BASE 0xC0200000
382#define CONFIG_SYS_DUIO_RANGE 0x00010000
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100383
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_NAND0_CS 2 /* NAND chip connected to CSx */
385#define CONFIG_SYS_NAND1_CS 3 /* NAND chip connected to CSx */
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100386/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_EBC_PB0AP 0x04017200
388#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100389
390/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_EBC_PB1AP 0x018003c0
392#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100393
394/* Memory Bank 2 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_EBC_PB2AP 0x018003c0
396#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND0_ADDR | 0x1c000)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100397
398/* Memory Bank 3 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_EBC_PB3AP 0x018003c0
400#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND1_ADDR | 0x1c000)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100401
402/* Memory Bank 4 (DUMEM, 1MB) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_EBC_PB4AP 0x018053c0
404#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_DUMEM_BASE | 0x18000)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100405
406/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_EBC_PB5AP 0x018053c0
408#define CONFIG_SYS_EBC_PB5CR (CONFIG_SYS_DUIO_BASE | 0x18000)
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100409
410/*
411 * NAND FLASH
412 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_MAX_NAND_DEVICE 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
415#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
416 CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100417
418/*
419 * Internal Definitions
420 *
421 * Boot Flags
422 */
423#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
424#define BOOTFLAG_WARM 0x02 /* Software reboot */
425
426#if defined(CONFIG_CMD_KGDB)
427#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
428#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
429#endif
430
Matthias Fuchs7c91f512008-03-30 18:01:15 +0200431#define CONFIG_AUTOSCRIPT 1
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100432
Matthias Fuchs35dd0252008-10-07 13:13:07 +0200433#define CONFIG_OF_LIBFDT
434#define CONFIG_OF_BOARD_SETUP
435
Matthias Fuchs1a3ac862008-01-17 10:53:08 +0100436#endif /* __CONFIG_H */