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wdenkcd0a9de2004-02-23 20:48:38 +00001/*
2 * (C) Copyright 2004
3 * Tolunay Orkun, Nextio Inc., torkun@nextio.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
Wolfgang Denk53677ef2008-05-20 16:00:29 +020036#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
wdenkcd0a9de2004-02-23 20:48:38 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_CSB272 1 /* on a Cogent CSB272 board */
wdenk4d13cba2004-03-14 14:09:05 +000039#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
wdenkcd0a9de2004-02-23 20:48:38 +000040#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */
41#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
42
Wolfgang Denk2ae18242010-10-06 09:05:45 +020043#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
44
wdenkcd0a9de2004-02-23 20:48:38 +000045/*
46 * OS Bootstrap configuration
47 *
48 */
49
50#if 0
51#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
52#else
53#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */
54#endif
55
56#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */
57
58#if 1
59#undef CONFIG_BOOTARGS
60#define CONFIG_BOOTCOMMAND \
61 "setenv bootargs console=ttyS0,38400 debug " \
62 "root=/dev/ram rw ramdisk_size=4096 " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010063 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenkcd0a9de2004-02-23 20:48:38 +000064 "bootm fe000000 fe100000"
65#endif
66
67#if 0
68#undef CONFIG_BOOTARGS
69#define CONFIG_BOOTCOMMAND \
70 "bootp; " \
71 "setenv bootargs console=ttyS0,38400 debug " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010072 "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
73 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenkcd0a9de2004-02-23 20:48:38 +000074 "bootm"
75#endif
76
77/*
Jon Loeliger2fd90ce2007-07-09 21:48:26 -050078 * BOOTP options
wdenkcd0a9de2004-02-23 20:48:38 +000079 */
Jon Loeliger2fd90ce2007-07-09 21:48:26 -050080#define CONFIG_BOOTP_SUBNETMASK
81#define CONFIG_BOOTP_GATEWAY
82#define CONFIG_BOOTP_HOSTNAME
83#define CONFIG_BOOTP_BOOTPATH
84#define CONFIG_BOOTP_BOOTFILESIZE
85#define CONFIG_BOOTP_DNS2
wdenkcd0a9de2004-02-23 20:48:38 +000086
Jon Loeliger37e4f242007-07-04 22:31:56 -050087
88/*
89 * Command line configuration.
90 */
91#include <config_cmd_default.h>
92
93#define CONFIG_CMD_ASKENV
94#define CONFIG_CMD_BEDBUG
95#define CONFIG_CMD_ELF
96#define CONFIG_CMD_IRQ
97#define CONFIG_CMD_I2C
98#define CONFIG_CMD_PCI
99#define CONFIG_CMD_DATE
100#define CONFIG_CMD_MII
101#define CONFIG_CMD_PING
102#define CONFIG_CMD_DHCP
103
wdenkcd0a9de2004-02-23 20:48:38 +0000104
105/*
106 * Serial download configuration
107 *
108 */
109#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkcd0a9de2004-02-23 20:48:38 +0000111
112/*
113 * KGDB Configuration
114 *
115 */
Jon Loeliger37e4f242007-07-04 22:31:56 -0500116#if defined(CONFIG_CMD_KGDB)
wdenkcd0a9de2004-02-23 20:48:38 +0000117#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
118#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
119#endif
120
121/*
122 * Miscellaneous configurable options
123 *
124 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
wdenkcd0a9de2004-02-23 20:48:38 +0000126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_LONGHELP /* undef to save memory */
128#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger37e4f242007-07-04 22:31:56 -0500129#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkcd0a9de2004-02-23 20:48:38 +0000131#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkcd0a9de2004-02-23 20:48:38 +0000133#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
135#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
136#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkcd0a9de2004-02-23 20:48:38 +0000137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
139#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkcd0a9de2004-02-23 20:48:38 +0000140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
143#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkcd0a9de2004-02-23 20:48:38 +0000144
145/*
146 * For booting Linux, the board info and command line data
147 * have to be in the first 8 MB of memory, since this is
148 * the maximum mapped by the Linux kernel during initialization.
149 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkcd0a9de2004-02-23 20:48:38 +0000151
152/*
153 * watchdog configuration
154 *
155 */
156#undef CONFIG_WATCHDOG /* watchdog disabled */
157
158/*
159 * UART configuration
160 *
161 */
Stefan Roese550650d2010-09-20 16:05:31 +0200162#define CONFIG_CONS_INDEX 1 /* Use UART0 */
163#define CONFIG_SYS_NS16550
164#define CONFIG_SYS_NS16550_SERIAL
165#define CONFIG_SYS_NS16550_REG_SIZE 1
166#define CONFIG_SYS_NS16550_CLK get_serial_clock()
167
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#undef CONFIG_SYS_BASE_BAUD
wdenkcd0a9de2004-02-23 20:48:38 +0000170#define CONFIG_BAUDRATE 38400 /* Default baud rate */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_BAUDRATE_TABLE \
wdenkcd0a9de2004-02-23 20:48:38 +0000172 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
173
174/*
175 * I2C configuration
176 *
177 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000178#define CONFIG_SYS_I2C
179#define CONFIG_SYS_I2C_PPC4XX
180#define CONFIG_SYS_I2C_PPC4XX_CH0
181#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
182#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F /* I2C slave address */
wdenkcd0a9de2004-02-23 20:48:38 +0000183
184/*
185 * MII PHY configuration
186 *
187 */
Ben Warren96e21f82008-10-27 23:50:15 -0700188#define CONFIG_PPC4xx_EMAC
wdenkcd0a9de2004-02-23 20:48:38 +0000189#define CONFIG_MII 1 /* MII PHY management */
190#define CONFIG_PHY_ADDR 0 /* PHY address */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200191#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
wdenkcd0a9de2004-02-23 20:48:38 +0000192 /* 32usec min. for LXT971A */
193#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
194
195/*
196 * RTC configuration
197 *
198 * Note that DS1307 RTC is limited to 100Khz I2C bus.
199 *
200 */
201#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */
202
203/*
204 * PCI stuff
205 *
206 */
207#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000208#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenkcd0a9de2004-02-23 20:48:38 +0000209#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
210#define PCI_HOST_FORCE 1 /* configure as pci host */
211#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
212
213#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
214#define CONFIG_PCI_PNP /* do pci plug-and-play */
215 /* resource configuration */
216#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
217#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
220#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
221#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
222#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
223#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
224#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
225#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
226#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenkcd0a9de2004-02-23 20:48:38 +0000227
228/*
229 * IDE stuff
230 *
231 */
232#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
233#undef CONFIG_IDE_LED /* no led for ide supported */
234#undef CONFIG_IDE_RESET /* no reset for ide supported */
235
236/*
237 * Environment configuration
238 *
239 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200240#define CONFIG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200241#undef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200242#undef CONFIG_ENV_IS_IN_EEPROM
wdenkcd0a9de2004-02-23 20:48:38 +0000243
244/*
245 * General Memory organization
246 *
247 * Start addresses for the final memory configuration
248 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkcd0a9de2004-02-23 20:48:38 +0000250 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_SDRAM_BASE 0x00000000
252#define CONFIG_SYS_FLASH_BASE 0xFE000000
253#define CONFIG_SYS_FLASH_SIZE 0x02000000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200254#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
256#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */
wdenkcd0a9de2004-02-23 20:48:38 +0000257
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
259#define CONFIG_SYS_RAMSTART
wdenkcd0a9de2004-02-23 20:48:38 +0000260#endif
261
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200262#if defined(CONFIG_ENV_IS_IN_FLASH)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200263#define CONFIG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */
264#define CONFIG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */
265#define CONFIG_ENV_SIZE 0x00001000 /* Size of Environment */
266#define CONFIG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */
wdenkcd0a9de2004-02-23 20:48:38 +0000267#endif
268
269/*
270 * FLASH Device configuration
271 *
272 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200274#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
276#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
277#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
278#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max # of sectors on one chip */
279#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
280#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
wdenkcd0a9de2004-02-23 20:48:38 +0000281
282/*
283 * On Chip Memory location/size
284 *
285 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
287#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
wdenkcd0a9de2004-02-23 20:48:38 +0000288
289/*
290 * Global info and initial stack
291 *
292 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200294#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200295#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkcd0a9de2004-02-23 20:48:38 +0000297
298/*
wdenkcd0a9de2004-02-23 20:48:38 +0000299 * Miscellaneous board specific definitions
300 *
301 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_I2C_PLL_ADDR 0x58 /* I2C address of AMIS FS6377-01 PLL */
wdenkeeb1b772004-03-23 22:53:55 +0000303#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */
wdenkcd0a9de2004-02-23 20:48:38 +0000304
wdenkcd0a9de2004-02-23 20:48:38 +0000305#endif /* __CONFIG_H */