Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 1 | /* |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 2 | * (C) Copyright 2007-2009 |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * |
| 5 | * based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr> |
| 6 | * |
| 7 | * (C) Copyright 2001 |
| 8 | * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net |
| 9 | * |
| 10 | * See file CREDITS for list of people who contributed to this |
| 11 | * project. |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or |
| 14 | * modify it under the terms of the GNU General Public License as |
| 15 | * published by the Free Software Foundation; either version 2 of |
| 16 | * the License, or (at your option) any later version. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 21 | * GNU General Public License for more details. |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License |
| 24 | * along with this program; if not, write to the Free Software |
| 25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 26 | * MA 02111-1307 USA |
| 27 | */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 28 | |
| 29 | #include <common.h> |
Stefan Roese | b36df56 | 2010-09-09 19:18:00 +0200 | [diff] [blame] | 30 | #include <asm/ppc4xx.h> |
| 31 | #include <asm/ppc4xx-i2c.h> |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 32 | #include <i2c.h> |
Peter Tyser | 61f2b38 | 2010-04-12 22:28:07 -0500 | [diff] [blame] | 33 | #include <asm/io.h> |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 34 | |
Wolfgang Denk | d87080b | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 35 | DECLARE_GLOBAL_DATA_PTR; |
| 36 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 37 | static inline struct ppc4xx_i2c *ppc4xx_get_i2c(int hwadapnr) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 38 | { |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 39 | unsigned long base; |
| 40 | |
| 41 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
| 42 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
| 43 | defined(CONFIG_460EX) || defined(CONFIG_460GT) |
| 44 | base = CONFIG_SYS_PERIPHERAL_BASE + 0x00000700 + (hwadapnr * 0x100); |
| 45 | #elif defined(CONFIG_440) || defined(CONFIG_405EX) |
| 46 | /* all remaining 440 variants */ |
| 47 | base = CONFIG_SYS_PERIPHERAL_BASE + 0x00000400 + (hwadapnr * 0x100); |
| 48 | #else |
| 49 | /* all 405 variants */ |
| 50 | base = 0xEF600500 + (hwadapnr * 0x100); |
| 51 | #endif |
| 52 | return (struct ppc4xx_i2c *)base; |
| 53 | } |
| 54 | |
| 55 | static void _i2c_bus_reset(struct i2c_adapter *adap) |
| 56 | { |
| 57 | struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr); |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 58 | int i; |
| 59 | u8 dc; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 60 | |
| 61 | /* Reset status register */ |
| 62 | /* write 1 in SCMP and IRQA to clear these fields */ |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 63 | out_8(&i2c->sts, 0x0A); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 64 | |
| 65 | /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */ |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 66 | out_8(&i2c->extsts, 0x8F); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 67 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 68 | /* Place chip in the reset state */ |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 69 | out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 70 | |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 71 | /* Check if bus is free */ |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 72 | dc = in_8(&i2c->directcntl); |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 73 | if (!DIRCTNL_FREE(dc)){ |
| 74 | /* Try to set bus free state */ |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 75 | out_8(&i2c->directcntl, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC); |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 76 | |
| 77 | /* Wait until we regain bus control */ |
| 78 | for (i = 0; i < 100; ++i) { |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 79 | dc = in_8(&i2c->directcntl); |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 80 | if (DIRCTNL_FREE(dc)) |
| 81 | break; |
| 82 | |
| 83 | /* Toggle SCL line */ |
| 84 | dc ^= IIC_DIRCNTL_SCC; |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 85 | out_8(&i2c->directcntl, dc); |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 86 | udelay(10); |
| 87 | dc ^= IIC_DIRCNTL_SCC; |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 88 | out_8(&i2c->directcntl, dc); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 89 | } |
| 90 | } |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 91 | |
| 92 | /* Remove reset */ |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 93 | out_8(&i2c->xtcntlss, 0); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 94 | } |
| 95 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 96 | static void ppc4xx_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 97 | { |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 98 | struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 99 | int val, divisor; |
| 100 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 101 | #ifdef CONFIG_SYS_I2C_INIT_BOARD |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 102 | /* |
| 103 | * Call board specific i2c bus reset routine before accessing the |
| 104 | * environment, which might be in a chip on that bus. For details |
| 105 | * about this problem see doc/I2C_Edge_Conditions. |
| 106 | */ |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame] | 107 | i2c_init_board(); |
| 108 | #endif |
| 109 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 110 | /* Handle possible failed I2C state */ |
| 111 | /* FIXME: put this into i2c_init_board()? */ |
| 112 | _i2c_bus_reset(adap); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 113 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 114 | /* clear lo master address */ |
| 115 | out_8(&i2c->lmadr, 0); |
Stefan Roese | 1a332da | 2010-03-29 15:30:46 +0200 | [diff] [blame] | 116 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 117 | /* clear hi master address */ |
| 118 | out_8(&i2c->hmadr, 0); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 119 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 120 | /* clear lo slave address */ |
| 121 | out_8(&i2c->lsadr, 0); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 122 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 123 | /* clear hi slave address */ |
| 124 | out_8(&i2c->hsadr, 0); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 125 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 126 | /* Clock divide Register */ |
| 127 | /* set divisor according to freq_opb */ |
| 128 | divisor = (get_OPB_freq() - 1) / 10000000; |
| 129 | if (divisor == 0) |
| 130 | divisor = 1; |
| 131 | out_8(&i2c->clkdiv, divisor); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 132 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 133 | /* no interrupts */ |
| 134 | out_8(&i2c->intrmsk, 0); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 135 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 136 | /* clear transfer count */ |
| 137 | out_8(&i2c->xfrcnt, 0); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 138 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 139 | /* clear extended control & stat */ |
| 140 | /* write 1 in SRC SRS SWC SWS to clear these fields */ |
| 141 | out_8(&i2c->xtcntlss, 0xF0); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 142 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 143 | /* Mode Control Register |
| 144 | Flush Slave/Master data buffer */ |
| 145 | out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 146 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 147 | val = in_8(&i2c->mdcntl); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 148 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 149 | /* Ignore General Call, slave transfers are ignored, |
| 150 | * disable interrupts, exit unknown bus state, enable hold |
| 151 | * SCL 100kHz normaly or FastMode for 400kHz and above |
| 152 | */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 153 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 154 | val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL; |
| 155 | if (speed >= 400000) |
| 156 | val |= IIC_MDCNTL_FSM; |
| 157 | out_8(&i2c->mdcntl, val); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 158 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 159 | /* clear control reg */ |
| 160 | out_8(&i2c->cntl, 0x00); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 161 | } |
| 162 | |
| 163 | /* |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 164 | * This code tries to use the features of the 405GP i2c |
| 165 | * controller. It will transfer up to 4 bytes in one pass |
| 166 | * on the loop. It only does out_8((u8 *)lbz) to the buffer when it |
| 167 | * is possible to do out16(lhz) transfers. |
| 168 | * |
| 169 | * cmd_type is 0 for write 1 for read. |
| 170 | * |
| 171 | * addr_len can take any value from 0-255, it is only limited |
| 172 | * by the char, we could make it larger if needed. If it is |
| 173 | * 0 we skip the address write cycle. |
| 174 | * |
| 175 | * Typical case is a Write of an addr followd by a Read. The |
| 176 | * IBM FAQ does not cover this. On the last byte of the write |
| 177 | * we don't set the creg CHT bit, and on the first bytes of the |
| 178 | * read we set the RPST bit. |
| 179 | * |
| 180 | * It does not support address only transfers, there must be |
| 181 | * a data part. If you want to write the address yourself, put |
| 182 | * it in the data pointer. |
| 183 | * |
| 184 | * It does not support transfer to/from address 0. |
| 185 | * |
| 186 | * It does not check XFRCNT. |
| 187 | */ |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 188 | static int _i2c_transfer(struct i2c_adapter *adap, |
| 189 | unsigned char cmd_type, |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 190 | unsigned char chip, |
| 191 | unsigned char addr[], |
| 192 | unsigned char addr_len, |
| 193 | unsigned char data[], |
| 194 | unsigned short data_len) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 195 | { |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 196 | struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr); |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 197 | u8 *ptr; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 198 | int reading; |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 199 | int tran, cnt; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 200 | int result; |
| 201 | int status; |
| 202 | int i; |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 203 | u8 creg; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 204 | |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 205 | if (data == 0 || data_len == 0) { |
| 206 | /* Don't support data transfer of no length or to address 0 */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 207 | printf( "i2c_transfer: bad call\n" ); |
| 208 | return IIC_NOK; |
| 209 | } |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 210 | if (addr && addr_len) { |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 211 | ptr = addr; |
| 212 | cnt = addr_len; |
| 213 | reading = 0; |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 214 | } else { |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 215 | ptr = data; |
| 216 | cnt = data_len; |
| 217 | reading = cmd_type; |
| 218 | } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 219 | |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 220 | /* Clear Stop Complete Bit */ |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 221 | out_8(&i2c->sts, IIC_STS_SCMP); |
| 222 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 223 | /* Check init */ |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 224 | i = 10; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 225 | do { |
| 226 | /* Get status */ |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 227 | status = in_8(&i2c->sts); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 228 | i--; |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 229 | } while ((status & IIC_STS_PT) && (i > 0)); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 230 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 231 | if (status & IIC_STS_PT) { |
| 232 | result = IIC_NOK_TOUT; |
| 233 | return(result); |
| 234 | } |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 235 | |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 236 | /* flush the Master/Slave Databuffers */ |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 237 | out_8(&i2c->mdcntl, in_8(&i2c->mdcntl) | |
| 238 | IIC_MDCNTL_FMDB | IIC_MDCNTL_FSDB); |
| 239 | |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 240 | /* need to wait 4 OPB clocks? code below should take that long */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 241 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 242 | /* 7-bit adressing */ |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 243 | out_8(&i2c->hmadr, 0); |
| 244 | out_8(&i2c->lmadr, chip); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 245 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 246 | tran = 0; |
| 247 | result = IIC_OK; |
| 248 | creg = 0; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 249 | |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 250 | while (tran != cnt && (result == IIC_OK)) { |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 251 | int bc,j; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 252 | |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 253 | /* |
| 254 | * Control register = |
| 255 | * Normal transfer, 7-bits adressing, Transfer up to |
| 256 | * bc bytes, Normal start, Transfer is a sequence of transfers |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 257 | */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 258 | creg |= IIC_CNTL_PT; |
| 259 | |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 260 | bc = (cnt - tran) > 4 ? 4 : cnt - tran; |
| 261 | creg |= (bc - 1) << 4; |
| 262 | /* if the real cmd type is write continue trans */ |
| 263 | if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt)) |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 264 | creg |= IIC_CNTL_CHT; |
| 265 | |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 266 | if (reading) { |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 267 | creg |= IIC_CNTL_READ; |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 268 | } else { |
| 269 | for(j = 0; j < bc; j++) { |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 270 | /* Set buffer */ |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 271 | out_8(&i2c->mdbuf, ptr[tran + j]); |
| 272 | } |
| 273 | } |
| 274 | out_8(&i2c->cntl, creg); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 275 | |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 276 | /* |
| 277 | * Transfer is in progress |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 278 | * we have to wait for upto 5 bytes of data |
| 279 | * 1 byte chip address+r/w bit then bc bytes |
| 280 | * of data. |
| 281 | * udelay(10) is 1 bit time at 100khz |
| 282 | * Doubled for slop. 20 is too small. |
| 283 | */ |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 284 | i = 2 * 5 * 8; |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 285 | do { |
| 286 | /* Get status */ |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 287 | status = in_8(&i2c->sts); |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 288 | udelay(10); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 289 | i--; |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 290 | } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) && |
| 291 | (i > 0)); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 292 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 293 | if (status & IIC_STS_ERR) { |
| 294 | result = IIC_NOK; |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 295 | status = in_8(&i2c->extsts); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 296 | /* Lost arbitration? */ |
| 297 | if (status & IIC_EXTSTS_LA) |
| 298 | result = IIC_NOK_LA; |
| 299 | /* Incomplete transfer? */ |
| 300 | if (status & IIC_EXTSTS_ICT) |
| 301 | result = IIC_NOK_ICT; |
| 302 | /* Transfer aborted? */ |
| 303 | if (status & IIC_EXTSTS_XFRA) |
| 304 | result = IIC_NOK_XFRA; |
| 305 | } else if ( status & IIC_STS_PT) { |
| 306 | result = IIC_NOK_TOUT; |
| 307 | } |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 308 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 309 | /* Command is reading => get buffer */ |
| 310 | if ((reading) && (result == IIC_OK)) { |
| 311 | /* Are there data in buffer */ |
| 312 | if (status & IIC_STS_MDBS) { |
| 313 | /* |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 314 | * even if we have data we have to wait 4OPB |
| 315 | * clocks for it to hit the front of the FIFO, |
| 316 | * after that we can just read. We should check |
| 317 | * XFCNT here and if the FIFO is full there is |
| 318 | * no need to wait. |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 319 | */ |
| 320 | udelay(1); |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 321 | for (j = 0; j < bc; j++) |
| 322 | ptr[tran + j] = in_8(&i2c->mdbuf); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 323 | } else |
| 324 | result = IIC_NOK_DATA; |
| 325 | } |
| 326 | creg = 0; |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 327 | tran += bc; |
| 328 | if (ptr == addr && tran == cnt) { |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 329 | ptr = data; |
| 330 | cnt = data_len; |
| 331 | tran = 0; |
| 332 | reading = cmd_type; |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 333 | if (reading) |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 334 | creg = IIC_CNTL_RPST; |
| 335 | } |
| 336 | } |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 337 | return result; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 338 | } |
| 339 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 340 | static int ppc4xx_i2c_probe(struct i2c_adapter *adap, uchar chip) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 341 | { |
| 342 | uchar buf[1]; |
| 343 | |
| 344 | buf[0] = 0; |
| 345 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 346 | /* |
| 347 | * What is needed is to send the chip address and verify that the |
| 348 | * address was <ACK>ed (i.e. there was a chip at that address which |
| 349 | * drove the data line low). |
| 350 | */ |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 351 | return (_i2c_transfer(adap, 1, chip << 1, 0, 0, buf, 1) != 0); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 352 | } |
| 353 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 354 | static int ppc4xx_i2c_transfer(struct i2c_adapter *adap, uchar chip, uint addr, |
| 355 | int alen, uchar *buffer, int len, int read) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 356 | { |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 357 | uchar xaddr[4]; |
| 358 | int ret; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 359 | |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 360 | if (alen > 4) { |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 361 | printf("I2C: addr len %d not supported\n", alen); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 362 | return 1; |
| 363 | } |
| 364 | |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 365 | if (alen > 0) { |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 366 | xaddr[0] = (addr >> 24) & 0xFF; |
| 367 | xaddr[1] = (addr >> 16) & 0xFF; |
| 368 | xaddr[2] = (addr >> 8) & 0xFF; |
| 369 | xaddr[3] = addr & 0xFF; |
| 370 | } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 371 | |
| 372 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 373 | #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 374 | /* |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 375 | * EEPROM chips that implement "address overflow" are ones |
| 376 | * like Catalyst 24WC04/08/16 which has 9/10/11 bits of |
| 377 | * address and the extra bits end up in the "chip address" |
| 378 | * bit slots. This makes a 24WC08 (1Kbyte) chip look like |
| 379 | * four 256 byte chips. |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 380 | * |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 381 | * Note that we consider the length of the address field to |
| 382 | * still be one byte because the extra address bits are |
| 383 | * hidden in the chip address. |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 384 | */ |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 385 | if (alen > 0) |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 386 | chip |= ((addr >> (alen * 8)) & |
| 387 | CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 388 | #endif |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 389 | ret = _i2c_transfer(adap, read, chip << 1, &xaddr[4 - alen], alen, |
| 390 | buffer, len); |
| 391 | if (ret) { |
Graeme Russ | e3e454c | 2011-08-29 02:14:05 +0000 | [diff] [blame] | 392 | printf("I2C %s: failed %d\n", read ? "read" : "write", ret); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 393 | return 1; |
| 394 | } |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 395 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 396 | return 0; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 397 | } |
| 398 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 399 | static int ppc4xx_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, |
| 400 | int alen, uchar *buffer, int len) |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 401 | { |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 402 | return ppc4xx_i2c_transfer(adap, chip, addr, alen, buffer, len, 1); |
Stefan Roese | eb5eb2b | 2009-11-19 14:03:17 +0100 | [diff] [blame] | 403 | } |
| 404 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 405 | static int ppc4xx_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, |
| 406 | int alen, uchar *buffer, int len) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 407 | { |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 408 | return ppc4xx_i2c_transfer(adap, chip, addr, alen, buffer, len, 0); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 409 | } |
| 410 | |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 411 | static unsigned int ppc4xx_i2c_set_bus_speed(struct i2c_adapter *adap, |
| 412 | unsigned int speed) |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 413 | { |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 414 | if (speed != adap->speed) |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 415 | return -1; |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 416 | return speed; |
Stefan Roese | 79b2d0b | 2007-02-20 10:27:08 +0100 | [diff] [blame] | 417 | } |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame^] | 418 | |
| 419 | /* |
| 420 | * Register ppc4xx i2c adapters |
| 421 | */ |
| 422 | #ifdef CONFIG_SYS_I2C_PPC4XX_CH0 |
| 423 | U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_0, ppc4xx_i2c_init, ppc4xx_i2c_probe, |
| 424 | ppc4xx_i2c_read, ppc4xx_i2c_write, |
| 425 | ppc4xx_i2c_set_bus_speed, |
| 426 | CONFIG_SYS_I2C_PPC4XX_SPEED_0, |
| 427 | CONFIG_SYS_I2C_PPC4XX_SLAVE_0, 0) |
| 428 | #endif |
| 429 | #ifdef CONFIG_SYS_I2C_PPC4XX_CH1 |
| 430 | U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_1, ppc4xx_i2c_init, ppc4xx_i2c_probe, |
| 431 | ppc4xx_i2c_read, ppc4xx_i2c_write, |
| 432 | ppc4xx_i2c_set_bus_speed, |
| 433 | CONFIG_SYS_I2C_PPC4XX_SPEED_1, |
| 434 | CONFIG_SYS_I2C_PPC4XX_SLAVE_1, 1) |
| 435 | #endif |