blob: 125f97d0044b323aa2a603417d7392b1356f4e6e [file] [log] [blame]
Masahiro Yamada252ed872015-03-12 13:24:39 +09001CONFIG_ARM=y
Masahiro Yamada5ca269a2015-03-16 16:43:24 +09002CONFIG_ARCH_ZYNQ=y
Michal Simek6ebf8a42016-12-16 11:57:17 +01003CONFIG_SYS_TEXT_BASE=0x4000000
Michal Simek0732d7c2017-12-13 10:35:06 +01004CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM010"
Michal Simek52b36fd2017-12-01 13:50:33 +01005CONFIG_SPL_STACK_R_ADDR=0x200000
Masahiro Yamadaf1ef2b62014-09-22 19:59:06 +09006CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
Michal Simek4c82ab92017-11-02 10:40:57 +01007CONFIG_DEBUG_UART=y
Michal Simeka5870512018-01-09 19:31:16 +01008CONFIG_DISTRO_DEFAULTS=y
Ruchika Gupta11a96622015-01-23 16:01:53 +05309CONFIG_FIT=y
Ruchika Gupta11a96622015-01-23 16:01:53 +053010CONFIG_FIT_SIGNATURE=y
Jagan Teki3788b452017-01-21 11:48:33 +010011CONFIG_FIT_VERBOSE=y
Michal Simek83144cd2018-01-09 17:41:37 +010012CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
Lokesh Vutla19a97472016-10-08 14:41:44 -040013# CONFIG_DISPLAY_CPUINFO is not set
Simon Glassc2ae7d82016-09-12 23:18:22 -060014CONFIG_SPL=y
Michal Simek52b36fd2017-12-01 13:50:33 +010015CONFIG_SPL_STACK_R=y
Heiko Schocherc20ae2f2016-10-06 07:55:15 +020016CONFIG_SPL_OS_BOOT=y
Siva Durga Prasad Paladuguc5ca2db2016-01-11 12:01:10 +053017CONFIG_SYS_PROMPT="Zynq> "
Joe Hershbergeref0f2f52015-06-22 16:15:30 -050018# CONFIG_CMD_FLASH is not set
Simon Glassfe7604a2017-05-17 03:25:21 -060019CONFIG_CMD_FPGA_LOADBP=y
20CONFIG_CMD_FPGA_LOADFS=y
21CONFIG_CMD_FPGA_LOADMK=y
22CONFIG_CMD_FPGA_LOADP=y
Thomas Choue4aa8ed2015-11-11 21:39:33 +080023CONFIG_CMD_GPIO=y
Tom Rini88663122017-08-14 19:58:53 -040024CONFIG_CMD_MMC=y
25CONFIG_CMD_SF=y
Joe Hershbergeref0f2f52015-06-22 16:15:30 -050026# CONFIG_CMD_SETEXPR is not set
Tom Rini78d1e1d2016-04-22 16:41:25 -040027CONFIG_CMD_TFTPPUT=y
Tom Rini89cb2b52016-04-24 17:29:26 -040028CONFIG_CMD_CACHE=y
Tom Rini89cb2b52016-04-24 17:29:26 -040029CONFIG_CMD_EXT4_WRITE=y
Tom Rini5dc4dfd2017-08-28 07:16:32 -040030CONFIG_ENV_IS_IN_SPI_FLASH=y
Masahiro Yamada739968f2015-07-17 20:26:06 +090031CONFIG_NET_RANDOM_ETHADDR=y
Nathan Rossi5c9b1d72016-01-08 03:00:46 +100032CONFIG_SPL_DM_SEQ_ALIAS=y
Michal Simek7fad6122017-11-03 15:53:56 +010033CONFIG_FPGA_XILINX=y
Michal Simek93561a32018-01-09 15:27:31 +010034CONFIG_DM_GPIO=y
Masahiro Yamadae1ce61f2016-12-07 22:10:28 +090035CONFIG_MMC_SDHCI=y
Michal Simek2e0583b2017-02-10 13:57:35 +010036CONFIG_MMC_SDHCI_ZYNQ=y
Joe Hershbergerc9bb9422015-06-22 16:15:29 -050037CONFIG_SPI_FLASH=y
Michal Simekdce7e112016-01-12 13:44:29 +010038CONFIG_SPI_FLASH_BAR=y
Michal Simekb2ff7fb2017-11-02 10:44:48 +010039CONFIG_SPI_FLASH_MACRONIX=y
Bin Meng68d53422015-11-25 05:34:54 -080040CONFIG_SPI_FLASH_SPANSION=y
41CONFIG_SPI_FLASH_STMICRO=y
42CONFIG_SPI_FLASH_SST=y
43CONFIG_SPI_FLASH_WINBOND=y
Vipul Kumar77217c42018-01-24 10:51:30 +053044CONFIG_PHY_MARVELL=y
45CONFIG_PHY_REALTEK=y
46CONFIG_PHY_XILINX=y
Michal Simek596e5782015-11-30 14:34:52 +010047CONFIG_ZYNQ_GEM=y
Michal Simek4c82ab92017-11-02 10:40:57 +010048CONFIG_DEBUG_UART_ZYNQ=y
49CONFIG_DEBUG_UART_BASE=0xe0001000
50CONFIG_DEBUG_UART_CLOCK=50000000
Michal Simek809704e2017-11-06 09:16:05 +010051CONFIG_ZYNQ_SERIAL=y
Bin Menge5d5d442015-11-25 05:34:53 -080052CONFIG_ZYNQ_SPI=y
Jagan Teki38a41672015-08-31 17:38:40 +053053CONFIG_ZYNQ_QSPI=y