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Stefan Roese17f50f222005-08-04 17:09:16 +02001/*
2 * (C) Copyright 2005
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Wolfgang Denkf901a832005-08-06 01:42:58 +020015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Stefan Roese17f50f222005-08-04 17:09:16 +020016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*----------------------------------------------------------------------------+
25 | FPGA registers and bit definitions
26 +----------------------------------------------------------------------------*/
27/*
28 * PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0.
29 * TLB initialization makes it correspond to logical address 0x80001FF0.
30 * => Done init_chip.s in bootlib
31 */
Wolfgang Denkf901a832005-08-06 01:42:58 +020032#define FPGA_BASE_ADDR 0x80002000
Stefan Roese17f50f222005-08-04 17:09:16 +020033
34/*----------------------------------------------------------------------------+
35 | Board Jumpers Setting Register
36 | Board Settings provided by jumpers
37 +----------------------------------------------------------------------------*/
Wolfgang Denkf901a832005-08-06 01:42:58 +020038#define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3)
Stefan Roese17f50f222005-08-04 17:09:16 +020039/* Boot from small flash */
Wolfgang Denkf901a832005-08-06 01:42:58 +020040#define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80
Stefan Roese17f50f222005-08-04 17:09:16 +020041/* Operational Flash versus SRAM position in Memory Map */
Wolfgang Denkf901a832005-08-06 01:42:58 +020042#define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40
43#define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40
44#define FPGA_SET_REG_SRAM_ABOVE 0x00
Stefan Roese17f50f222005-08-04 17:09:16 +020045/* Boot From NAND Flash */
Wolfgang Denkf901a832005-08-06 01:42:58 +020046#define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40
47#define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00
Stefan Roese17f50f222005-08-04 17:09:16 +020048/* On Board PCI Arbiter Select */
Wolfgang Denkf901a832005-08-06 01:42:58 +020049#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10
50#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00
Stefan Roese17f50f222005-08-04 17:09:16 +020051
52/*----------------------------------------------------------------------------+
53 | Functions Selection Register 1
54 +----------------------------------------------------------------------------*/
Wolfgang Denkf901a832005-08-06 01:42:58 +020055#define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4)
56#define FPGA_SEL_1_REG_PHY_MASK 0xE0
57#define FPGA_SEL_1_REG_MII 0x80
58#define FPGA_SEL_1_REG_RMII 0x40
59#define FPGA_SEL_1_REG_SMII 0x20
60#define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */
61#define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */
62#define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */
63#define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */
64#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */
65#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */
Stefan Roese17f50f222005-08-04 17:09:16 +020066
67/*----------------------------------------------------------------------------+
68 | Functions Selection Register 2
69 +----------------------------------------------------------------------------*/
Wolfgang Denkf901a832005-08-06 01:42:58 +020070#define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5)
71#define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */
72#define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */
73#define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */
74#define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */
75#define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */
76#define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */
77#define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */
78 /* 1 = TC - output from 440EP */
79#define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */
80 /* 1 = TC (output from 440EP) */
81#define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */
82#define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */
83#define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */
Stefan Roese17f50f222005-08-04 17:09:16 +020084
85/*----------------------------------------------------------------------------+
86 | Functions Selection Register 3
87 +----------------------------------------------------------------------------*/
Wolfgang Denkf901a832005-08-06 01:42:58 +020088#define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6)
89#define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */
90#define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70
91#define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */
92#define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */
93#define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */
94#define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */
95#define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */
96#define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */
Stefan Roese17f50f222005-08-04 17:09:16 +020097
98/*----------------------------------------------------------------------------+
99 | Soft Reset Register
100 +----------------------------------------------------------------------------*/
Wolfgang Denkf901a832005-08-06 01:42:58 +0200101#define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7)
102#define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */
103#define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */
104#define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */
105#define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */
106#define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */
107#define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */
Stefan Roese17f50f222005-08-04 17:09:16 +0200108
109
110/*----------------------------------------------------------------------------+
111| SDR Configuration registers
112+----------------------------------------------------------------------------*/
113/* Serial Device Strap Reg 0 */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200114#define SDR0_SDSTP0 0x0020
Stefan Roese17f50f222005-08-04 17:09:16 +0200115/* Serial Device Strap Reg 1 */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200116#define SDR0_SDSTP1 0x0021
Stefan Roese17f50f222005-08-04 17:09:16 +0200117/* Serial Device Strap Reg 2 */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200118#define SDR0_SDSTP2 SDR0_STRP2
Stefan Roese17f50f222005-08-04 17:09:16 +0200119/* Serial Device Strap Reg 3 */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200120#define SDR0_SDSTP3 SDR0_STRP3
Stefan Roese17f50f222005-08-04 17:09:16 +0200121
Wolfgang Denkf901a832005-08-06 01:42:58 +0200122#define sdr_pstrp0 0x0040
Stefan Roese17f50f222005-08-04 17:09:16 +0200123
Wolfgang Denkf901a832005-08-06 01:42:58 +0200124#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */
125#define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */
126#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */
127#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
Stefan Roese17f50f222005-08-04 17:09:16 +0200128
Wolfgang Denkf901a832005-08-06 01:42:58 +0200129#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */
130#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
131#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */
132#define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */
Stefan Roese17f50f222005-08-04 17:09:16 +0200133
134/* Serial Device Enabled - Addr = 0xA8 */
135#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
136/* Serial Device Enabled - Addr = 0xA4 */
137#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
138
139/* Pin Straps Reg */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200140#define SDR0_PSTRP0 0x0040
141#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
Stefan Roese17f50f222005-08-04 17:09:16 +0200142
143#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
144#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
145#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
146#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
147#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
148#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
149#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
150#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
151
152/*----------------------------------------------------------------------------+
153| EBC Configuration Register - EBC0_CFG
154+----------------------------------------------------------------------------*/
155/* External Bus Three-State Control */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200156#define EBC0_CFG_EBTC_DRIVEN 0x80000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200157/* Device-Paced Time-out Disable */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200158#define EBC0_CFG_PTD_ENABLED 0x00000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200159/* Ready Timeout Count */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200160#define EBC0_CFG_RTC_MASK 0x38000000
161#define EBC0_CFG_RTC_16PERCLK 0x00000000
162#define EBC0_CFG_RTC_32PERCLK 0x08000000
163#define EBC0_CFG_RTC_64PERCLK 0x10000000
164#define EBC0_CFG_RTC_128PERCLK 0x18000000
165#define EBC0_CFG_RTC_256PERCLK 0x20000000
166#define EBC0_CFG_RTC_512PERCLK 0x28000000
167#define EBC0_CFG_RTC_1024PERCLK 0x30000000
168#define EBC0_CFG_RTC_2048PERCLK 0x38000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200169/* External Master Priority Low */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200170#define EBC0_CFG_EMPL_LOW 0x00000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200171#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
172#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
Wolfgang Denkf901a832005-08-06 01:42:58 +0200173#define EBC0_CFG_EMPL_HIGH 0x06000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200174/* External Master Priority High */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200175#define EBC0_CFG_EMPH_LOW 0x00000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200176#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
177#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
Wolfgang Denkf901a832005-08-06 01:42:58 +0200178#define EBC0_CFG_EMPH_HIGH 0x01800000
Stefan Roese17f50f222005-08-04 17:09:16 +0200179/* Chip Select Three-State Control */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200180#define EBC0_CFG_CSTC_DRIVEN 0x00400000
Stefan Roese17f50f222005-08-04 17:09:16 +0200181/* Burst Prefetch */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200182#define EBC0_CFG_BPF_ONEDW 0x00000000
183#define EBC0_CFG_BPF_TWODW 0x00100000
184#define EBC0_CFG_BPF_FOURDW 0x00200000
Stefan Roese17f50f222005-08-04 17:09:16 +0200185/* External Master Size */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200186#define EBC0_CFG_EMS_8BIT 0x00000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200187/* Power Management Enable */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200188#define EBC0_CFG_PME_DISABLED 0x00000000
189#define EBC0_CFG_PME_ENABLED 0x00020000
Stefan Roese17f50f222005-08-04 17:09:16 +0200190/* Power Management Timer */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200191#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
Stefan Roese17f50f222005-08-04 17:09:16 +0200192
193/*----------------------------------------------------------------------------+
194| Peripheral Bank Configuration Register - EBC0_BnCR
195+----------------------------------------------------------------------------*/
196/* BAS - Base Address Select */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200197#define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
Stefan Roese17f50f222005-08-04 17:09:16 +0200198/* BS - Bank Size */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200199#define EBC0_BNCR_BS_MASK 0x000E0000
200#define EBC0_BNCR_BS_1MB 0x00000000
201#define EBC0_BNCR_BS_2MB 0x00020000
202#define EBC0_BNCR_BS_4MB 0x00040000
203#define EBC0_BNCR_BS_8MB 0x00060000
204#define EBC0_BNCR_BS_16MB 0x00080000
205#define EBC0_BNCR_BS_32MB 0x000A0000
206#define EBC0_BNCR_BS_64MB 0x000C0000
207#define EBC0_BNCR_BS_128MB 0x000E0000
Stefan Roese17f50f222005-08-04 17:09:16 +0200208/* BU - Bank Usage */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200209#define EBC0_BNCR_BU_MASK 0x00018000
210#define EBC0_BNCR_BU_RO 0x00008000
211#define EBC0_BNCR_BU_WO 0x00010000
212#define EBC0_BNCR_BU_RW 0x00018000
Stefan Roese17f50f222005-08-04 17:09:16 +0200213/* BW - Bus Width */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200214#define EBC0_BNCR_BW_MASK 0x00006000
215#define EBC0_BNCR_BW_8BIT 0x00000000
216#define EBC0_BNCR_BW_16BIT 0x00002000
217#define EBC0_BNCR_BW_32BIT 0x00004000
Stefan Roese17f50f222005-08-04 17:09:16 +0200218
219/*----------------------------------------------------------------------------+
220| Peripheral Bank Access Parameters - EBC0_BnAP
221+----------------------------------------------------------------------------*/
222/* Burst Mode Enable */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200223#define EBC0_BNAP_BME_ENABLED 0x80000000
224#define EBC0_BNAP_BME_DISABLED 0x00000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200225/* Transfert Wait */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200226#define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */
Stefan Roese17f50f222005-08-04 17:09:16 +0200227/* Chip Select On Timing */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200228#define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */
Stefan Roese17f50f222005-08-04 17:09:16 +0200229/* Output Enable On Timing */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200230#define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */
Stefan Roese17f50f222005-08-04 17:09:16 +0200231/* Write Back Enable On Timing */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200232#define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */
Stefan Roese17f50f222005-08-04 17:09:16 +0200233/* Write Back Enable Off Timing */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200234#define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */
Stefan Roese17f50f222005-08-04 17:09:16 +0200235/* Transfert Hold */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200236#define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */
Stefan Roese17f50f222005-08-04 17:09:16 +0200237/* PerReady Enable */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200238#define EBC0_BNAP_RE_ENABLED 0x00000100
239#define EBC0_BNAP_RE_DISABLED 0x00000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200240/* Sample On Ready */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200241#define EBC0_BNAP_SOR_DELAYED 0x00000000
Stefan Roese17f50f222005-08-04 17:09:16 +0200242#define EBC0_BNAP_SOR_NOT_DELAYED 0x00000080
243/* Byte Enable Mode */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200244#define EBC0_BNAP_BEM_WRITEONLY 0x00000000
245#define EBC0_BNAP_BEM_RW 0x00000040
Stefan Roese17f50f222005-08-04 17:09:16 +0200246/* Parity Enable */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200247#define EBC0_BNAP_PEN_DISABLED 0x00000000
248#define EBC0_BNAP_PEN_ENABLED 0x00000020
Stefan Roese17f50f222005-08-04 17:09:16 +0200249
250/*----------------------------------------------------------------------------+
251| Define Boot devices
252+----------------------------------------------------------------------------*/
253/* */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200254#define BOOT_FROM_SMALL_FLASH 0x00
255#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
256#define BOOT_FROM_NAND_FLASH0 0x02
257#define BOOT_FROM_PCI 0x03
258#define BOOT_DEVICE_UNKNOWN 0x04
Stefan Roese17f50f222005-08-04 17:09:16 +0200259
260
Wolfgang Denkf901a832005-08-06 01:42:58 +0200261#define PVR_POWERPC_440EP_PASS1 0x42221850
262#define PVR_POWERPC_440EP_PASS2 0x422218D3
Stefan Roese17f50f222005-08-04 17:09:16 +0200263
264#define TRUE 1
265#define FALSE 0
266
Wolfgang Denkf901a832005-08-06 01:42:58 +0200267#define GPIO_GROUP_MAX 2
268#define GPIO_MAX 32
269#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
270#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
271#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
272#define GPIO_MASK 0xC0000000 /* GPIO_MASK */
273#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
274 /* For the other GPIO number, you must shift */
Stefan Roese17f50f222005-08-04 17:09:16 +0200275
Wolfgang Denkf901a832005-08-06 01:42:58 +0200276#define GPIO0 0
277#define GPIO1 1
Stefan Roese17f50f222005-08-04 17:09:16 +0200278
279
Wolfgang Denkf901a832005-08-06 01:42:58 +0200280/*#define MAX_SELECTION_NB CORE_NB */
281#define MAX_CORE_SELECT_NB 22
Stefan Roese17f50f222005-08-04 17:09:16 +0200282
283/*----------------------------------------------------------------------------+
284 | PPC440EP GPIOs addresses.
285 +----------------------------------------------------------------------------*/
Wolfgang Denkf901a832005-08-06 01:42:58 +0200286#define GPIO0_REAL 0xEF600B00
Stefan Roese17f50f222005-08-04 17:09:16 +0200287
Wolfgang Denkf901a832005-08-06 01:42:58 +0200288#define GPIO1_REAL 0xEF600C00
Stefan Roese17f50f222005-08-04 17:09:16 +0200289
290/* Offsets */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200291#define GPIOx_OR 0x00 /* GPIO Output Register */
292#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
293#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
294#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
295#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
296#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
297#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
298#define GPIOx_IR 0x1C /* GPIO Input Register */
299#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
300#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
301#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
302#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
303#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
304#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
305#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
306#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
307#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
Stefan Roese17f50f222005-08-04 17:09:16 +0200308
309/* GPIO0 */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200310#define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L)
311#define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H)
312#define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L)
313#define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H)
314#define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L)
315#define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L)
Stefan Roese17f50f222005-08-04 17:09:16 +0200316
317/* GPIO1 */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200318#define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L)
319#define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H)
320#define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L)
321#define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H)
322#define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L)
323#define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L)
Stefan Roese17f50f222005-08-04 17:09:16 +0200324
Wolfgang Denkf901a832005-08-06 01:42:58 +0200325#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
326#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
327#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
328#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
329#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
Stefan Roese17f50f222005-08-04 17:09:16 +0200330
331
332/*----------------------------------------------------------------------------+
Wolfgang Denkf901a832005-08-06 01:42:58 +0200333 | XX XX
Stefan Roese17f50f222005-08-04 17:09:16 +0200334 |
335 | XXXXXX XXX XX XXX XXX
Wolfgang Denkf901a832005-08-06 01:42:58 +0200336 | XX XX X XX XX XX
337 | XX XX X XX XX XX
338 | XX XX XX XX XX
Stefan Roese17f50f222005-08-04 17:09:16 +0200339 | XXXXXX XXX XXX XXXX XXXX
340 +----------------------------------------------------------------------------*/
341/*----------------------------------------------------------------------------+
342 | Defines
343 +----------------------------------------------------------------------------*/
344typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN,
Wolfgang Denkf901a832005-08-06 01:42:58 +0200345 ZMII_CONFIGURATION_IS_MII,
346 ZMII_CONFIGURATION_IS_RMII,
347 ZMII_CONFIGURATION_IS_SMII
Stefan Roese17f50f222005-08-04 17:09:16 +0200348} zmii_config_t;
349
350/*----------------------------------------------------------------------------+
351 | Declare Configuration values
352 +----------------------------------------------------------------------------*/
353typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t;
354typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t;
355typedef enum config_list { IIC_CORE,
Wolfgang Denkf901a832005-08-06 01:42:58 +0200356 SCP_CORE,
357 DMA_CHANNEL_AB,
358 UIC_4_9,
359 USB2_HOST,
360 DMA_CHANNEL_CD,
361 USB2_DEVICE,
362 PACKET_REJ_FUNC_AVAIL,
363 USB1_DEVICE,
364 EBC_MASTER,
365 NAND_FLASH,
366 UART_CORE0,
367 UART_CORE1,
368 UART_CORE2,
369 UART_CORE3,
370 MII_SEL,
371 RMII_SEL,
372 SMII_SEL,
373 PACKET_REJ_FUNC_EN,
374 UIC_0_3,
375 USB1_HOST,
376 PCI_PATCH,
377 CORE_NB
Stefan Roese17f50f222005-08-04 17:09:16 +0200378} core_list_t;
379
380typedef enum block3_value { B3_V1, B3_V2, B3_V3, B3_V4, B3_V5,
Wolfgang Denkf901a832005-08-06 01:42:58 +0200381 B3_V6, B3_V7, B3_V8, B3_V9, B3_V10,
382 B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
383 B3_V16, B3_VALUE_UNKNOWN
Stefan Roese17f50f222005-08-04 17:09:16 +0200384} block3_value_t;
385
386typedef enum config_validity { CONFIG_IS_VALID,
Wolfgang Denkf901a832005-08-06 01:42:58 +0200387 CONFIG_IS_INVALID
Stefan Roese17f50f222005-08-04 17:09:16 +0200388} config_validity_t;