blob: fdd89969554150ba235d2a34bd20d7f47f9ad91e [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Tom Warrenefc05ae2011-01-27 10:58:07 +00002/*
Tom Warren52a8b822012-05-22 12:19:25 +00003 * (C) Copyright 2010-2012
Tom Warrenefc05ae2011-01-27 10:58:07 +00004 * NVIDIA Corporation <www.nvidia.com>
Tom Warrenefc05ae2011-01-27 10:58:07 +00005 */
6
Tom Warrenf01b6312012-12-11 13:34:18 +00007#ifndef _TEGRA20_COMMON_H_
8#define _TEGRA20_COMMON_H_
9#include "tegra-common.h"
10
11/*
12 * NS16550 Configuration
13 */
14#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
Simon Glass649d0ff2012-04-02 13:19:03 +000015
Tom Warrenf01b6312012-12-11 13:34:18 +000016/*
17 * Miscellaneous configurable options
18 */
Jonathan Hunterf16e3112019-02-12 16:03:14 +000019#define CONFIG_STACKBASE 0x03800000 /* 56MB */
Tom Warrenf01b6312012-12-11 13:34:18 +000020
21/*-----------------------------------------------------------------------
22 * Physical Memory Map
23 */
Tom Warrenf01b6312012-12-11 13:34:18 +000024
25/*
26 * Memory layout for where various images get loaded by boot scripts:
27 *
28 * scriptaddr can be pretty much anywhere that doesn't conflict with something
29 * else. Put it above BOOTMAPSZ to eliminate conflicts.
30 *
Stephen Warrenf940c722014-02-05 09:24:59 -070031 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
32 * something else. Put it above BOOTMAPSZ to eliminate conflicts.
33 *
Tom Warrenf01b6312012-12-11 13:34:18 +000034 * kernel_addr_r must be within the first 128M of RAM in order for the
35 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
36 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
37 * should not overlap that area, or the kernel will have to copy itself
38 * somewhere else before decompression. Similarly, the address of any other
39 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
Jonathan Hunterf16e3112019-02-12 16:03:14 +000040 * this up to 32M allows for a sizable kernel to be decompressed below the
Tom Warrenf01b6312012-12-11 13:34:18 +000041 * compressed load address.
42 *
Jonathan Hunterf16e3112019-02-12 16:03:14 +000043 * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
44 * the compressed kernel to be up to 32M too.
Tom Warrenf01b6312012-12-11 13:34:18 +000045 *
Jonathan Hunterf16e3112019-02-12 16:03:14 +000046 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
Tom Warrenf01b6312012-12-11 13:34:18 +000047 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
48 */
Stephen Warren48cfca22015-04-01 15:40:53 -060049#define CONFIG_LOADADDR 0x01000000
Tom Warrenf01b6312012-12-11 13:34:18 +000050#define MEM_LAYOUT_ENV_SETTINGS \
51 "scriptaddr=0x10000000\0" \
Stephen Warrenf940c722014-02-05 09:24:59 -070052 "pxefile_addr_r=0x10100000\0" \
Stephen Warren48cfca22015-04-01 15:40:53 -060053 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
Peter Robinson632fb972020-04-02 00:28:54 +010054 "fdtfile=" FDTFILE "\0" \
Jonathan Hunterf16e3112019-02-12 16:03:14 +000055 "fdt_addr_r=0x03000000\0" \
56 "ramdisk_addr_r=0x03100000\0"
Tom Warrenf01b6312012-12-11 13:34:18 +000057
58/* Defines for SPL */
Tom Warrenf01b6312012-12-11 13:34:18 +000059#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
60#define CONFIG_SPL_STACK 0x000ffffc
61
Simon Glassad166172012-10-17 13:24:56 +000062/* Align LCD to 1MB boundary */
63#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
64
Tom Warren29f3e3f2012-09-04 17:00:24 -070065#ifdef CONFIG_TEGRA_LP0
Simon Glass649d0ff2012-04-02 13:19:03 +000066#define TEGRA_LP0_ADDR 0x1C406000
67#define TEGRA_LP0_SIZE 0x2000
68#define TEGRA_LP0_VEC \
Tom Warrenf01b6312012-12-11 13:34:18 +000069 "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
Marek Vasut51926d52012-09-23 17:41:25 +020070 "@" __stringify(TEGRA_LP0_ADDR) " "
Simon Glass649d0ff2012-04-02 13:19:03 +000071#else
72#define TEGRA_LP0_VEC
73#endif
74
Simon Glass02910912012-02-27 10:52:51 +000075/*
76 * This parameter affects a TXFILLTUNING field that controls how much data is
77 * sent to the latency fifo before it is sent to the wire. Without this
78 * parameter, the default (2) causes occasional Data Buffer Errors in OUT
79 * packets depending on the buffer address and size.
80 */
Peter Robinsoncba0ae62018-09-16 18:22:58 +010081#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
Simon Glass02910912012-02-27 10:52:51 +000082#define CONFIG_EHCI_IS_TDI
Simon Glass02910912012-02-27 10:52:51 +000083
Simon Glass0dd84082012-07-29 20:53:30 +000084#define CONFIG_SYS_NAND_SELF_INIT
Lucas Stacha833b952012-10-07 11:29:38 +000085#define CONFIG_SYS_NAND_ONFI_DETECTION
Simon Glass0dd84082012-07-29 20:53:30 +000086
Tom Warrenf01b6312012-12-11 13:34:18 +000087#endif /* _TEGRA20_COMMON_H_ */