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Jon Loeliger25d83d72007-04-11 16:51:02 -05001/*
Kumar Gala6525d512010-07-08 22:37:44 -05002 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
Jon Loeliger25d83d72007-04-11 16:51:02 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <command.h>
Ed Swarthout837f1ba2007-07-27 01:50:51 -050025#include <pci.h>
Jon Loeliger25d83d72007-04-11 16:51:02 -050026#include <asm/processor.h>
Kumar Gala1167a2f2008-08-26 08:02:30 -050027#include <asm/mmu.h>
Jon Loeliger25d83d72007-04-11 16:51:02 -050028#include <asm/immap_85xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050029#include <asm/fsl_pci.h>
Kumar Gala1167a2f2008-08-26 08:02:30 -050030#include <asm/fsl_ddr_sdram.h>
Kumar Gala5d27e022010-12-15 04:55:20 -060031#include <asm/fsl_serdes.h>
Kumar Gala56a92702007-08-30 16:18:18 -050032#include <asm/io.h>
Jon Loeliger25d83d72007-04-11 16:51:02 -050033#include <miiphy.h>
Kumar Galaaddce572007-11-26 17:12:24 -060034#include <libfdt.h>
35#include <fdt_support.h>
Andy Fleming063c1262011-04-08 02:10:54 -050036#include <fsl_mdio.h>
Andy Fleming216f2a72008-08-31 16:33:29 -050037#include <tsec.h>
Ben Warren0b252f52008-08-31 21:41:08 -070038#include <netdev.h>
Jon Loeliger25d83d72007-04-11 16:51:02 -050039
Andy Fleming216f2a72008-08-31 16:33:29 -050040#include "../common/sgmii_riser.h"
Jon Loeliger25d83d72007-04-11 16:51:02 -050041
Jon Loeliger25d83d72007-04-11 16:51:02 -050042int checkboard (void)
43{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Becky Brucef51cdaf2010-06-17 11:37:20 -050045 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
Kumar Gala6bb5b412009-07-14 22:42:01 -050047 u8 vboot;
48 u8 *pixis_base = (u8 *)PIXIS_BASE;
Jon Loeliger25d83d72007-04-11 16:51:02 -050049
Wolfgang Denk2f152782007-05-05 18:23:11 +020050 if ((uint)&gur->porpllsr != 0xe00e0000) {
Wolfgang Denk9b55a252008-07-11 01:16:00 +020051 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
Jon Loeliger25d83d72007-04-11 16:51:02 -050052 }
Kumar Gala6bb5b412009-07-14 22:42:01 -050053 printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
54 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
55 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
56 in_8(pixis_base + PIXIS_PVER));
57
58 vboot = in_8(pixis_base + PIXIS_VBOOT);
59 if (vboot & PIXIS_VBOOT_FMAP)
60 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
61 else
62 puts ("Promjet\n");
Jon Loeliger25d83d72007-04-11 16:51:02 -050063
Ed Swarthout837f1ba2007-07-27 01:50:51 -050064 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
65 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
66 ecm->eedr = 0xffffffff; /* Clear ecm errors */
67 ecm->eeer = 0xffffffff; /* Enable ecm errors */
68
Jon Loeliger25d83d72007-04-11 16:51:02 -050069 return 0;
70}
71
Ed Swarthout837f1ba2007-07-27 01:50:51 -050072#ifdef CONFIG_PCI1
73static struct pci_controller pci1_hose;
74#endif
75
Ed Swarthout837f1ba2007-07-27 01:50:51 -050076#ifdef CONFIG_PCIE3
77static struct pci_controller pcie3_hose;
78#endif
79
Kumar Gala645d5a72009-11-04 10:22:26 -060080void pci_init_board(void)
Ed Swarthout837f1ba2007-07-27 01:50:51 -050081{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kumar Gala64a16862010-12-17 06:01:24 -060083 struct fsl_pci_info pci_info;
Kumar Gala645d5a72009-11-04 10:22:26 -060084 u32 devdisr, pordevsr, io_sel;
85 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
86 int first_free_busno = 0;
Ed Swarthout837f1ba2007-07-27 01:50:51 -050087
Kumar Gala645d5a72009-11-04 10:22:26 -060088 int pcie_ep, pcie_configured;
89
90 devdisr = in_be32(&gur->devdisr);
91 pordevsr = in_be32(&gur->pordevsr);
92 porpllsr = in_be32(&gur->porpllsr);
93 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
94
95 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
Ed Swarthout837f1ba2007-07-27 01:50:51 -050096
Kumar Gala645d5a72009-11-04 10:22:26 -060097 puts("\n");
Ed Swarthout837f1ba2007-07-27 01:50:51 -050098
99#ifdef CONFIG_PCIE3
Kumar Gala5d27e022010-12-15 04:55:20 -0600100 pcie_configured = is_serdes_configured(PCIE3);
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500101
Kumar Gala645d5a72009-11-04 10:22:26 -0600102 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
Kumar Gala64a16862010-12-17 06:01:24 -0600103 /* contains both PCIE3 MEM & IO space */
104 set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
105 LAW_TRGT_IF_PCIE_3);
106 SET_STD_PCIE_INFO(pci_info, 3);
107 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);
108
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500109 /* outbound memory */
Kumar Gala645d5a72009-11-04 10:22:26 -0600110 pci_set_region(&pcie3_hose.regions[0],
Kumar Gala10795f42008-12-02 16:08:36 -0600111 CONFIG_SYS_PCIE3_MEM_BUS2,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112 CONFIG_SYS_PCIE3_MEM_PHYS2,
113 CONFIG_SYS_PCIE3_MEM_SIZE2,
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500114 PCI_REGION_MEM);
Kumar Gala645d5a72009-11-04 10:22:26 -0600115
116 pcie3_hose.region_count = 1;
Kumar Gala64a16862010-12-17 06:01:24 -0600117
Peter Tyser8ca78f22010-10-29 17:59:24 -0500118 printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
119 pcie_ep ? "Endpoint" : "Root Complex",
Kumar Gala64a16862010-12-17 06:01:24 -0600120 pci_info.regs);
121 first_free_busno = fsl_pci_init_port(&pci_info,
Kumar Gala645d5a72009-11-04 10:22:26 -0600122 &pcie3_hose, first_free_busno);
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500123
Kumar Gala56a92702007-08-30 16:18:18 -0500124 /*
125 * Activate ULI1575 legacy chip by performing a fake
126 * memory access. Needed to make ULI RTC work.
127 */
Kumar Gala10795f42008-12-02 16:08:36 -0600128 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500129 } else {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500130 printf("PCIE3: disabled\n");
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500131 }
Kumar Gala645d5a72009-11-04 10:22:26 -0600132 puts("\n");
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500133#else
Kumar Gala645d5a72009-11-04 10:22:26 -0600134 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500135#endif
136
137#ifdef CONFIG_PCIE1
Kumar Gala64a16862010-12-17 06:01:24 -0600138 SET_STD_PCIE_INFO(pci_info, 1);
139 first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500140#else
Kumar Gala64a16862010-12-17 06:01:24 -0600141 setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500142#endif
143
144#ifdef CONFIG_PCIE2
Kumar Gala64a16862010-12-17 06:01:24 -0600145 SET_STD_PCIE_INFO(pci_info, 2);
146 first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500147#else
Kumar Gala64a16862010-12-17 06:01:24 -0600148 setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500149#endif
150
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500151#ifdef CONFIG_PCI1
Kumar Gala645d5a72009-11-04 10:22:26 -0600152 pci_speed = 66666000;
153 pci_32 = 1;
154 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
155 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500156
157 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
Kumar Gala64a16862010-12-17 06:01:24 -0600158 SET_STD_PCI_INFO(pci_info, 1);
159 set_next_law(pci_info.mem_phys,
160 law_size_bits(pci_info.mem_size), pci_info.law);
161 set_next_law(pci_info.io_phys,
162 law_size_bits(pci_info.io_size), pci_info.law);
163
164 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
Peter Tyser8ca78f22010-10-29 17:59:24 -0500165 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500166 (pci_32) ? 32 : 64,
167 (pci_speed == 33333000) ? "33" :
168 (pci_speed == 66666000) ? "66" : "unknown",
169 pci_clk_sel ? "sync" : "async",
170 pci_agent ? "agent" : "host",
171 pci_arb ? "arbiter" : "external-arbiter",
Kumar Gala64a16862010-12-17 06:01:24 -0600172 pci_info.regs);
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500173
Kumar Gala64a16862010-12-17 06:01:24 -0600174 first_free_busno = fsl_pci_init_port(&pci_info,
Kumar Gala645d5a72009-11-04 10:22:26 -0600175 &pci1_hose, first_free_busno);
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500176 } else {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500177 printf("PCI: disabled\n");
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500178 }
Kumar Gala645d5a72009-11-04 10:22:26 -0600179
180 puts("\n");
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500181#else
Kumar Gala645d5a72009-11-04 10:22:26 -0600182 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500183#endif
184}
185
Jon Loeliger25d83d72007-04-11 16:51:02 -0500186int last_stage_init(void)
187{
188 return 0;
189}
190
191
192unsigned long
193get_board_sys_clk(ulong dummy)
194{
195 u8 i, go_bit, rd_clks;
196 ulong val = 0;
Kumar Gala048e7ef2009-07-22 10:12:39 -0500197 u8 *pixis_base = (u8 *)PIXIS_BASE;
Jon Loeliger25d83d72007-04-11 16:51:02 -0500198
Kumar Gala048e7ef2009-07-22 10:12:39 -0500199 go_bit = in_8(pixis_base + PIXIS_VCTL);
Jon Loeliger25d83d72007-04-11 16:51:02 -0500200 go_bit &= 0x01;
201
Kumar Gala048e7ef2009-07-22 10:12:39 -0500202 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
Jon Loeliger25d83d72007-04-11 16:51:02 -0500203 rd_clks &= 0x1C;
204
205 /*
206 * Only if both go bit and the SCLK bit in VCFGEN0 are set
207 * should we be using the AUX register. Remember, we also set the
208 * GO bit to boot from the alternate bank on the on-board flash
209 */
210
211 if (go_bit) {
212 if (rd_clks == 0x1c)
Kumar Gala048e7ef2009-07-22 10:12:39 -0500213 i = in_8(pixis_base + PIXIS_AUX);
Jon Loeliger25d83d72007-04-11 16:51:02 -0500214 else
Kumar Gala048e7ef2009-07-22 10:12:39 -0500215 i = in_8(pixis_base + PIXIS_SPD);
Jon Loeliger25d83d72007-04-11 16:51:02 -0500216 } else {
Kumar Gala048e7ef2009-07-22 10:12:39 -0500217 i = in_8(pixis_base + PIXIS_SPD);
Jon Loeliger25d83d72007-04-11 16:51:02 -0500218 }
219
220 i &= 0x07;
221
222 switch (i) {
223 case 0:
224 val = 33333333;
225 break;
226 case 1:
227 val = 40000000;
228 break;
229 case 2:
230 val = 50000000;
231 break;
232 case 3:
233 val = 66666666;
234 break;
235 case 4:
236 val = 83000000;
237 break;
238 case 5:
239 val = 100000000;
240 break;
241 case 6:
242 val = 133333333;
243 break;
244 case 7:
245 val = 166666666;
246 break;
247 }
248
249 return val;
250}
251
Andy Fleming063c1262011-04-08 02:10:54 -0500252
253#define MIIM_CIS8204_SLED_CON 0x1b
254#define MIIM_CIS8204_SLEDCON_INIT 0x1115
255/*
256 * Hack to write all 4 PHYs with the LED values
257 */
258int board_phy_config(struct phy_device *phydev)
259{
260 static int do_once;
261 uint phyid;
262 struct mii_dev *bus = phydev->bus;
263
264 if (do_once)
265 return 0;
266
267 for (phyid = 0; phyid < 4; phyid++)
268 bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
269 MIIM_CIS8204_SLEDCON_INIT);
270
271 do_once = 1;
272
273 return 0;
274}
275
276
Andy Fleming216f2a72008-08-31 16:33:29 -0500277int board_eth_init(bd_t *bis)
278{
Ben Warren0b252f52008-08-31 21:41:08 -0700279#ifdef CONFIG_TSEC_ENET
Andy Fleming063c1262011-04-08 02:10:54 -0500280 struct fsl_pq_mdio_info mdio_info;
Andy Fleming216f2a72008-08-31 16:33:29 -0500281 struct tsec_info_struct tsec_info[2];
Andy Fleming216f2a72008-08-31 16:33:29 -0500282 int num = 0;
283
284#ifdef CONFIG_TSEC1
285 SET_STD_TSEC_INFO(tsec_info[num], 1);
Kumar Gala058d7dc2010-12-16 14:28:06 -0600286 if (is_serdes_configured(SGMII_TSEC1)) {
287 puts("eTSEC1 is in sgmii mode.\n");
Andy Fleming216f2a72008-08-31 16:33:29 -0500288 tsec_info[num].flags |= TSEC_SGMII;
Kumar Gala058d7dc2010-12-16 14:28:06 -0600289 }
Andy Fleming216f2a72008-08-31 16:33:29 -0500290 num++;
291#endif
292#ifdef CONFIG_TSEC3
293 SET_STD_TSEC_INFO(tsec_info[num], 3);
Kumar Gala058d7dc2010-12-16 14:28:06 -0600294 if (is_serdes_configured(SGMII_TSEC3)) {
295 puts("eTSEC3 is in sgmii mode.\n");
Andy Fleming216f2a72008-08-31 16:33:29 -0500296 tsec_info[num].flags |= TSEC_SGMII;
Kumar Gala058d7dc2010-12-16 14:28:06 -0600297 }
Andy Fleming216f2a72008-08-31 16:33:29 -0500298 num++;
299#endif
300
301 if (!num) {
302 printf("No TSECs initialized\n");
303
304 return 0;
305 }
306
Kumar Gala058d7dc2010-12-16 14:28:06 -0600307 if (is_serdes_configured(SGMII_TSEC1) ||
308 is_serdes_configured(SGMII_TSEC3)) {
Andy Fleming216f2a72008-08-31 16:33:29 -0500309 fsl_sgmii_riser_init(tsec_info, num);
Kumar Gala058d7dc2010-12-16 14:28:06 -0600310 }
Andy Fleming216f2a72008-08-31 16:33:29 -0500311
Andy Fleming063c1262011-04-08 02:10:54 -0500312 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
313 mdio_info.name = DEFAULT_MII_NAME;
314 fsl_pq_mdio_init(bis, &mdio_info);
Andy Fleming216f2a72008-08-31 16:33:29 -0500315
316 tsec_eth_init(bis, tsec_info, num);
Andy Fleming216f2a72008-08-31 16:33:29 -0500317#endif
Ben Warren0b252f52008-08-31 21:41:08 -0700318 return pci_eth_init(bis);
319}
Andy Fleming216f2a72008-08-31 16:33:29 -0500320
Kumar Galaaddce572007-11-26 17:12:24 -0600321#if defined(CONFIG_OF_BOARD_SETUP)
Kumar Gala2dba0de2008-10-21 08:28:33 -0500322void ft_board_setup(void *blob, bd_t *bd)
Jon Loeliger25d83d72007-04-11 16:51:02 -0500323{
Wolfgang Denk2f152782007-05-05 18:23:11 +0200324 ft_cpu_setup(blob, bd);
Jon Loeliger25d83d72007-04-11 16:51:02 -0500325
Kumar Gala6525d512010-07-08 22:37:44 -0500326 FT_FSL_PCI_SETUP;
Kumar Gala2dba0de2008-10-21 08:28:33 -0500327
Andy Flemingfeede8b2008-12-05 20:10:22 -0600328#ifdef CONFIG_FSL_SGMII_RISER
329 fsl_sgmii_riser_fdt_fixup(blob);
330#endif
Jon Loeliger25d83d72007-04-11 16:51:02 -0500331}
332#endif