blob: 1d88e6504bcfc8c15e86772d853becedf0cc4f9f [file] [log] [blame]
Andy Fleming063c1262011-04-08 02:10:54 -05001/*
Claudiu Manoil5be00a02013-09-30 12:44:43 +03002 * Copyright 2009-2010, 2013 Freescale Semiconductor, Inc.
Andy Fleming063c1262011-04-08 02:10:54 -05003 * Jun-jie Zhang <b18070@freescale.com>
4 * Mingkai Hu <Mingkai.hu@freescale.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Andy Fleming063c1262011-04-08 02:10:54 -05007 */
8#include <common.h>
9#include <miiphy.h>
10#include <phy.h>
11#include <fsl_mdio.h>
12#include <asm/io.h>
13#include <asm/errno.h>
14#include <asm/fsl_enet.h>
15
Claudiu Manoil5be00a02013-09-30 12:44:43 +030016void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
Andy Fleming063c1262011-04-08 02:10:54 -050017 int dev_addr, int regnum, int value)
18{
19 int timeout = 1000000;
20
21 out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
22 out_be32(&phyregs->miimcon, value);
23 asm("sync");
24
25 while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--)
26 ;
27}
28
Claudiu Manoil5be00a02013-09-30 12:44:43 +030029int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
Andy Fleming063c1262011-04-08 02:10:54 -050030 int dev_addr, int regnum)
31{
32 int value;
33 int timeout = 1000000;
34
35 /* Put the address of the phy, and the register
36 * number into MIIMADD */
37 out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
38
39 /* Clear the command register, and wait */
40 out_be32(&phyregs->miimcom, 0);
41 asm("sync");
42
43 /* Initiate a read command, and wait */
44 out_be32(&phyregs->miimcom, MIIMCOM_READ_CYCLE);
45 asm("sync");
46
47 /* Wait for the the indication that the read is done */
48 while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
49 && timeout--)
50 ;
51
52 /* Grab the value read from the PHY */
53 value = in_be32(&phyregs->miimstat);
54
55 return value;
56}
57
58static int fsl_pq_mdio_reset(struct mii_dev *bus)
59{
Claudiu Manoil5be00a02013-09-30 12:44:43 +030060 struct tsec_mii_mng __iomem *regs =
61 (struct tsec_mii_mng __iomem *)bus->priv;
Andy Fleming063c1262011-04-08 02:10:54 -050062
63 /* Reset MII (due to new addresses) */
64 out_be32(&regs->miimcfg, MIIMCFG_RESET_MGMT);
65
66 out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);
67
68 while (in_be32(&regs->miimind) & MIIMIND_BUSY)
69 ;
70
71 return 0;
72}
73
74int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum)
75{
Claudiu Manoil5be00a02013-09-30 12:44:43 +030076 struct tsec_mii_mng __iomem *phyregs =
77 (struct tsec_mii_mng __iomem *)bus->priv;
Andy Fleming063c1262011-04-08 02:10:54 -050078
79 return tsec_local_mdio_read(phyregs, addr, dev_addr, regnum);
80}
81
82int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
83 u16 value)
84{
Claudiu Manoil5be00a02013-09-30 12:44:43 +030085 struct tsec_mii_mng __iomem *phyregs =
86 (struct tsec_mii_mng __iomem *)bus->priv;
Andy Fleming063c1262011-04-08 02:10:54 -050087
88 tsec_local_mdio_write(phyregs, addr, dev_addr, regnum, value);
89
90 return 0;
91}
92
93int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info)
94{
95 struct mii_dev *bus = mdio_alloc();
96
97 if (!bus) {
98 printf("Failed to allocate FSL MDIO bus\n");
99 return -1;
100 }
101
102 bus->read = tsec_phy_read;
103 bus->write = tsec_phy_write;
104 bus->reset = fsl_pq_mdio_reset;
105 sprintf(bus->name, info->name);
106
Claudiu Manoil5be00a02013-09-30 12:44:43 +0300107 bus->priv = (void *)info->regs;
Andy Fleming063c1262011-04-08 02:10:54 -0500108
109 return mdio_register(bus);
110}