blob: dea061abee9d007a764a1071326840257534e845 [file] [log] [blame]
Lunsheng Wangb0e32942005-07-29 10:20:29 -05001/*
2 * (C) Copyright 2002,2003 Motorola,Inc.
3 * Modified by Lunsheng Wang, lunsheng@sohu.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* mpc8540eval board configuration file */
25/* please refer to doc/README.mpc85xxads for more info */
26/* make sure you change the MAC address and other network params first,
27 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32/* High Level Configuration Options */
33#define CONFIG_BOOKE 1 /* BOOKE */
34#define CONFIG_E500 1 /* BOOKE e500 family */
35#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
36#define CONFIG_MPC8540 1 /* MPC8540 specific */
37#define CONFIG_MPC8540EVAL 1 /* MPC8540EVAL board specific */
38
39#undef CONFIG_PCI /* pci ethernet support */
40#define CONFIG_TSEC_ENET /* tsec ethernet support */
41#define CONFIG_ENV_OVERWRITE
42#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
43#undef CONFIG_DDR_ECC /* only for ECC DDR module */
44#define CONFIG_DDR_DLL /* possible DLL fix needed */
45
46/* Using Localbus SDRAM to emulate flash before we can program the flash,
47 * normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
48 * Not availabe for EVAL board
49 */
50#undef CONFIG_RAM_AS_FLASH
51
52/* sysclk for MPC8540EVAL */
53#if defined(CONFIG_SYSCLK_66M)
Jon Loeligerde1d0a62005-08-01 13:20:47 -050054 /*
55 * the oscillator on board is 66Mhz
56 * can also get 66M clock from external PCI
57 */
58 #define CONFIG_SYS_CLK_FREQ 66000000
Lunsheng Wangb0e32942005-07-29 10:20:29 -050059#else
Jon Loeligerde1d0a62005-08-01 13:20:47 -050060 #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
Lunsheng Wangb0e32942005-07-29 10:20:29 -050061#endif
62
63/* below can be toggled for performance analysis. otherwise use default */
64#define CONFIG_L2_CACHE /* toggle L2 cache */
65#undef CONFIG_BTB /* toggle branch predition */
66#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
67
68#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
69
70#undef CFG_DRAM_TEST /* memory test, takes time */
71#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
72#define CFG_MEMTEST_END 0x00400000
73
74#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
75#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
76#endif
77
78/*
79 * Base addresses -- Note these are effective addresses where the
80 * actual resources get mapped (not physical addresses)
81 */
82#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
83#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
84#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
85
86#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
87#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
88#define CFG_SDRAM_SIZE 256 /* DDR is now 256MB */
89
90#if defined(CONFIG_RAM_AS_FLASH)
91#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
92#else
93#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
94#endif
95#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 0MB */
96
97#if defined(CONFIG_RAM_AS_FLASH)
98#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
99#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */
100#else /* Boot from real Flash */
101#define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
102#define CFG_BR0_PRELIM 0xff801001 /* port size 16bit */
103#endif
104
105#define CFG_OR0_PRELIM 0xff806f67 /* 8MB Flash */
106#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
107#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
108#undef CFG_FLASH_CHECKSUM
109#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms)*/
110#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/
111#define CFG_FLASH_CFI 1
112
113#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
114
115#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
116#define CFG_RAMBOOT
117#else
118#undef CFG_RAMBOOT
119#endif
120
121#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
122
123/* Here some DDR setting should be added */
124
125
126#undef CONFIG_CLOCKS_IN_MHZ
127
128/* local bus definitions */
129#define CFG_BR2_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
130#define CFG_OR2_PRELIM 0xfc006901
131#define CFG_LBC_LCRR 0x00030004 /* local bus freq divider*/
132#define CFG_LBC_LBCR 0x00000000
133#define CFG_LBC_LSRT 0x20000000
134#define CFG_LBC_MRTPR 0x20000000
135#define CFG_LBC_LSDMR_1 0x2861b723
136#define CFG_LBC_LSDMR_2 0x0861b723
137#define CFG_LBC_LSDMR_3 0x0861b723
138#define CFG_LBC_LSDMR_4 0x1861b723
139#define CFG_LBC_LSDMR_5 0x4061b723
140
141#if defined(CONFIG_RAM_AS_FLASH)
142#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
143#else
144#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
145#endif
146#define CFG_OR4_PRELIM 0xffffe1f1
147#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
148
149#define CONFIG_L1_INIT_RAM
150#define CFG_INIT_RAM_LOCK 1
151#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
152#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
153
154#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
155#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
156#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
157
158#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
159#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
160
161/* Serial Port */
162#define CONFIG_CONS_INDEX 1
163#undef CONFIG_SERIAL_SOFTWARE_FIFO
164#define CFG_NS16550
165#define CFG_NS16550_SERIAL
166#define CFG_NS16550_REG_SIZE 1
167#define CFG_NS16550_CLK get_bus_freq(0)
168#define CONFIG_BAUDRATE 115200
169
170#define CFG_BAUDRATE_TABLE \
171 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
172
173#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
174#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
175
176/* Use the HUSH parser */
177#define CFG_HUSH_PARSER
178#ifdef CFG_HUSH_PARSER
179#define CFG_PROMPT_HUSH_PS2 "> "
180#endif
181
Jon Loeliger20476722006-10-20 15:50:15 -0500182/*
183 * I2C
184 */
185#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
186#define CONFIG_HARD_I2C /* I2C with hardware support*/
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500187#undef CONFIG_SOFT_I2C /* I2C bit-banged */
188#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
189#define CFG_I2C_SLAVE 0x7F
190#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
Jon Loeliger20476722006-10-20 15:50:15 -0500191#define CFG_I2C_OFFSET 0x3000
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500192
193/* General PCI */
194#define CFG_PCI_MEM_BASE 0x80000000
195#define CFG_PCI_MEM_PHYS 0x80000000
196#define CFG_PCI_MEM_SIZE 0x20000000
197#define CFG_PCI_IO_BASE 0xe2000000
198
199#if defined(CONFIG_PCI)
200#define CONFIG_NET_MULTI
201#undef CONFIG_EEPRO100
202#define CONFIG_TULIP
203#define CONFIG_PCI_PNP /* do pci plug-and-play */
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500204#if !defined(CONFIG_PCI_PNP)
205#define PCI_ENET0_IOADDR 0xe0000000
206#define PCI_ENET0_MEMADDR 0xe0000000
207#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
208#endif
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500209#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
210#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
211#define CFG_PCI_SUBSYS_DEVICEID 0x0008
212#elif defined(CONFIG_TSEC_ENET)
213#define CONFIG_NET_MULTI 1
214#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500215#define CONFIG_TSEC1 1
216#define CONFIG_TSEC1_NAME "TSEC0"
217#define CONFIG_TSEC2 1
218#define CONFIG_TSEC2_NAME "TSEC1"
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500219#define CONFIG_MPC85XX_FEC 1
220#define CONFIG_MPC85XX_FEC_NAME "FEC"
221#define TSEC1_PHY_ADDR 7
222#define TSEC2_PHY_ADDR 4
223#define FEC_PHY_ADDR 2
224#define TSEC1_PHYIDX 0
225#define TSEC2_PHYIDX 0
226#define FEC_PHYIDX 0
227/* Options are: TSEC[0-1], FEC */
228#define CONFIG_ETHPRIME "TSEC0"
229
230#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500231#define INTEL_LXT971_PHY 1
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500232#endif
233
234#undef DEBUG
235
236/* Environment */
237#ifndef CFG_RAMBOOT
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500238#if defined(CONFIG_RAM_AS_FLASH)
239#define CFG_ENV_IS_NOWHERE
240#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
241#define CFG_ENV_SIZE 0x2000
242#else
243#define CFG_ENV_IS_IN_FLASH 1
244#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
245#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
246#endif
247#define CFG_ENV_SIZE 0x2000
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500248#else
249/* #define CFG_NO_FLASH 1 */ /* Flash is not usable now */
250#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
251#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
252#define CFG_ENV_SIZE 0x2000
253#endif
254
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500255#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"
256#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
257#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
258
259#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
260#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
261
Jon Loeliger2835e512007-06-13 13:22:08 -0500262
263/*
264 * Command line configuration.
265 */
266#include <config_cmd_default.h>
267
268#define CONFIG_CMD_PING
269#define CONFIG_CMD_I2C
270
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500271#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500272 #define CONFIG_CMD_PCI
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500273#endif
274
Jon Loeliger2835e512007-06-13 13:22:08 -0500275#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
276 #undef CONFIG_CMD_ENV
277 #undef CONFIG_CMD_LOADS
278#endif
279
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500280
281#undef CONFIG_WATCHDOG /* watchdog disabled */
282
283/*
284 * Miscellaneous configurable options
285 */
286#define CFG_LONGHELP /* undef to save memory */
287#define CFG_LOAD_ADDR 0x2000000 /* default load address */
288#define CFG_PROMPT "MPC8540EVAL=> "/* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500289#if defined(CONFIG_CMD_KGDB)
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500290#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
291#else
292#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
293#endif
294#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
295#define CFG_MAXARGS 16 /* max number of command args */
296#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
297#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
298
299/*
300 * For booting Linux, the board info and command line data
301 * have to be in the first 8 MB of memory, since this is
302 * the maximum mapped by the Linux kernel during initialization.
303 */
304#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
305
306/* Cache Configuration */
307#define CFG_DCACHE_SIZE 32768
308#define CFG_CACHELINE_SIZE 32
Jon Loeliger2835e512007-06-13 13:22:08 -0500309#if defined(CONFIG_CMD_KGDB)
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500310#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
311#endif
312
313/*
314 * Internal Definitions
315 *
316 * Boot Flags
317 */
318#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
319#define BOOTFLAG_WARM 0x02 /* Software reboot */
320
Jon Loeliger2835e512007-06-13 13:22:08 -0500321#if defined(CONFIG_CMD_KGDB)
Lunsheng Wangb0e32942005-07-29 10:20:29 -0500322#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
323#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
324#endif
325
326/*****************************/
327/* Environment Configuration */
328/*****************************/
329/* The mac addresses for all ethernet interface */
330/* NOTE: change below for your network setting!!! */
331#if defined(CONFIG_TSEC_ENET)
332#define CONFIG_ETHADDR 00:01:af:07:9b:8a
333#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
334#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
335#endif
336
337#define CONFIG_ROOTPATH /nfsroot
338#define CONFIG_BOOTFILE your.uImage
339
340#define CONFIG_SERVERIP 192.168.101.1
341#define CONFIG_IPADDR 192.168.101.11
342#define CONFIG_GATEWAYIP 192.168.101.0
343#define CONFIG_NETMASK 255.255.255.0
344
345#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
346
347#define CONFIG_HOSTNAME MPC8540EVAL
348
349#endif /* __CONFIG_H */