blob: a2ba6eefc57493332cc65e52f23d1586e0688741 [file] [log] [blame]
Jagan Teki0d47bc72018-12-22 21:32:49 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun50i-a64-ccu.h>
Jagan Teki99ba4302019-01-18 22:18:13 +053013#include <dt-bindings/reset/sun50i-a64-ccu.h>
Jagan Teki0d47bc72018-12-22 21:32:49 +053014
15static const struct ccu_clk_gate a64_gates[] = {
16 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
17 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
18 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
19 [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
20 [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
21
Jagan Teki4acc7112018-12-30 21:29:24 +053022 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
23 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
24 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
25 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
26 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
27
Jagan Teki0d47bc72018-12-22 21:32:49 +053028 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
29 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
30 [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
31 [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
32 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
33 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
34};
35
Jagan Teki99ba4302019-01-18 22:18:13 +053036static const struct ccu_reset a64_resets[] = {
37 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
38 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
39 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
40
41 [RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
42 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
43 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),
44 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
45 [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
Jagan Teki8606f962018-12-30 21:37:31 +053046
47 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
48 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
49 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
50 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
51 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
Jagan Teki99ba4302019-01-18 22:18:13 +053052};
53
Jagan Teki0d47bc72018-12-22 21:32:49 +053054static const struct ccu_desc a64_ccu_desc = {
55 .gates = a64_gates,
Jagan Teki99ba4302019-01-18 22:18:13 +053056 .resets = a64_resets,
Jagan Teki0d47bc72018-12-22 21:32:49 +053057};
58
Jagan Teki99ba4302019-01-18 22:18:13 +053059static int a64_clk_bind(struct udevice *dev)
60{
61 return sunxi_reset_bind(dev, ARRAY_SIZE(a64_resets));
62}
63
Jagan Teki0d47bc72018-12-22 21:32:49 +053064static const struct udevice_id a64_ccu_ids[] = {
65 { .compatible = "allwinner,sun50i-a64-ccu",
66 .data = (ulong)&a64_ccu_desc },
67 { }
68};
69
70U_BOOT_DRIVER(clk_sun50i_a64) = {
71 .name = "sun50i_a64_ccu",
72 .id = UCLASS_CLK,
73 .of_match = a64_ccu_ids,
74 .priv_auto_alloc_size = sizeof(struct ccu_priv),
75 .ops = &sunxi_clk_ops,
76 .probe = sunxi_clk_probe,
Jagan Teki99ba4302019-01-18 22:18:13 +053077 .bind = a64_clk_bind,
Jagan Teki0d47bc72018-12-22 21:32:49 +053078};