| Wolfgang Denk | f11033e | 2007-01-15 13:41:04 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007 |
| 3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <common.h> |
| 25 | |
| 26 | #if (CONFIG_COMMANDS & CFG_CMD_NAND) |
| 27 | |
| 28 | #include <nand.h> |
| 29 | #include <asm/processor.h> |
| 30 | |
| 31 | #define readb(addr) *(volatile u_char *)(addr) |
| 32 | #define readl(addr) *(volatile u_long *)(addr) |
| 33 | #define writeb(d,addr) *(volatile u_char *)(addr) = (d) |
| 34 | |
| 35 | #define SC3_NAND_ALE 29 /* GPIO PIN 3 */ |
| 36 | #define SC3_NAND_CLE 30 /* GPIO PIN 2 */ |
| 37 | #define SC3_NAND_CE 27 /* GPIO PIN 5 */ |
| 38 | |
| 39 | static void *sc3_io_base; |
| 40 | static void *sc3_control_base = (void *)0xEF600700; |
| 41 | |
| 42 | static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd) |
| 43 | { |
| 44 | switch (cmd) { |
| 45 | case NAND_CTL_SETCLE: |
| 46 | set_bit (SC3_NAND_CLE, sc3_control_base); |
| 47 | break; |
| 48 | case NAND_CTL_CLRCLE: |
| 49 | clear_bit (SC3_NAND_CLE, sc3_control_base); |
| 50 | break; |
| 51 | |
| 52 | case NAND_CTL_SETALE: |
| 53 | set_bit (SC3_NAND_ALE, sc3_control_base); |
| 54 | break; |
| 55 | case NAND_CTL_CLRALE: |
| 56 | clear_bit (SC3_NAND_ALE, sc3_control_base); |
| 57 | break; |
| 58 | |
| 59 | case NAND_CTL_SETNCE: |
| 60 | set_bit (SC3_NAND_CE, sc3_control_base); |
| 61 | break; |
| 62 | case NAND_CTL_CLRNCE: |
| 63 | clear_bit (SC3_NAND_CE, sc3_control_base); |
| 64 | break; |
| 65 | } |
| 66 | } |
| 67 | |
| 68 | static int sc3_nand_dev_ready(struct mtd_info *mtd) |
| 69 | { |
| 70 | if (!(readl(sc3_control_base + 0x1C) & 0x4000)) |
| 71 | return 0; |
| 72 | return 1; |
| 73 | } |
| 74 | |
| 75 | static void sc3_select_chip(struct mtd_info *mtd, int chip) |
| 76 | { |
| 77 | clear_bit (SC3_NAND_CE, sc3_control_base); |
| 78 | } |
| 79 | |
| 80 | int board_nand_init(struct nand_chip *nand) |
| 81 | { |
| 82 | nand->eccmode = NAND_ECC_SOFT; |
| 83 | |
| 84 | sc3_io_base = (void *) CFG_NAND_BASE; |
| 85 | /* Set address of NAND IO lines (Using Linear Data Access Region) */ |
| 86 | nand->IO_ADDR_R = (void __iomem *) sc3_io_base; |
| 87 | nand->IO_ADDR_W = (void __iomem *) sc3_io_base; |
| 88 | /* Reference hardware control function */ |
| 89 | nand->hwcontrol = sc3_nand_hwcontrol; |
| 90 | nand->dev_ready = sc3_nand_dev_ready; |
| 91 | nand->select_chip = sc3_select_chip; |
| 92 | return 0; |
| 93 | } |
| 94 | #endif |