blob: 1bc77a3b499788803f125a94d5855c198ee9f634 [file] [log] [blame]
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301/**
2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/slab.h>
21#include <linux/spinlock.h>
22#include <linux/platform_device.h>
23#include <linux/pm_runtime.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/list.h>
27#include <linux/dma-mapping.h>
28
29#include <linux/usb/ch9.h>
30#include <linux/usb/gadget.h>
31#include <linux/usb/composite.h>
32
33#include "core.h"
34#include "debug.h"
35#include "gadget.h"
36#include "io.h"
37
38static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
39static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
40 struct dwc3_ep *dep, struct dwc3_request *req);
41
42static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
43{
44 switch (state) {
45 case EP0_UNCONNECTED:
46 return "Unconnected";
47 case EP0_SETUP_PHASE:
48 return "Setup Phase";
49 case EP0_DATA_PHASE:
50 return "Data Phase";
51 case EP0_STATUS_PHASE:
52 return "Status Phase";
53 default:
54 return "UNKNOWN";
55 }
56}
57
58static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
59 u32 len, u32 type)
60{
61 struct dwc3_gadget_ep_cmd_params params;
62 struct dwc3_trb *trb;
63 struct dwc3_ep *dep;
64
65 int ret;
66
67 dep = dwc->eps[epnum];
68 if (dep->flags & DWC3_EP_BUSY) {
69 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
70 return 0;
71 }
72
73 trb = dwc->ep0_trb;
74
75 trb->bpl = lower_32_bits(buf_dma);
76 trb->bph = upper_32_bits(buf_dma);
77 trb->size = len;
78 trb->ctrl = type;
79
80 trb->ctrl |= (DWC3_TRB_CTRL_HWO
81 | DWC3_TRB_CTRL_LST
82 | DWC3_TRB_CTRL_IOC
83 | DWC3_TRB_CTRL_ISP_IMI);
84
85 memset(&params, 0, sizeof(params));
86 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
87 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
88
89 trace_dwc3_prepare_trb(dep, trb);
90
91 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
92 DWC3_DEPCMD_STARTTRANSFER, &params);
93 if (ret < 0) {
94 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
95 dep->name);
96 return ret;
97 }
98
99 dep->flags |= DWC3_EP_BUSY;
100 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
101 dep->number);
102
103 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
104
105 return 0;
106}
107
108static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
109 struct dwc3_request *req)
110{
111 struct dwc3 *dwc = dep->dwc;
112
113 req->request.actual = 0;
114 req->request.status = -EINPROGRESS;
115 req->epnum = dep->number;
116
117 list_add_tail(&req->list, &dep->request_list);
118
119 /*
120 * Gadget driver might not be quick enough to queue a request
121 * before we get a Transfer Not Ready event on this endpoint.
122 *
123 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
124 * flag is set, it's telling us that as soon as Gadget queues the
125 * required request, we should kick the transfer here because the
126 * IRQ we were waiting for is long gone.
127 */
128 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
129 unsigned direction;
130
131 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
132
133 if (dwc->ep0state != EP0_DATA_PHASE) {
134 dev_WARN(dwc->dev, "Unexpected pending request\n");
135 return 0;
136 }
137
138 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
139
140 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
141 DWC3_EP0_DIR_IN);
142
143 return 0;
144 }
145
146 /*
147 * In case gadget driver asked us to delay the STATUS phase,
148 * handle it here.
149 */
150 if (dwc->delayed_status) {
151 unsigned direction;
152
153 direction = !dwc->ep0_expect_in;
154 dwc->delayed_status = false;
155 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
156
157 if (dwc->ep0state == EP0_STATUS_PHASE)
158 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
159 else
160 dwc3_trace(trace_dwc3_ep0,
161 "too early for delayed status");
162
163 return 0;
164 }
165
166 /*
167 * Unfortunately we have uncovered a limitation wrt the Data Phase.
168 *
169 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
170 * come before issueing Start Transfer command, but if we do, we will
171 * miss situations where the host starts another SETUP phase instead of
172 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
173 * Layer Compliance Suite.
174 *
175 * The problem surfaces due to the fact that in case of back-to-back
176 * SETUP packets there will be no XferNotReady(DATA) generated and we
177 * will be stuck waiting for XferNotReady(DATA) forever.
178 *
179 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
180 * it tells us to start Data Phase right away. It also mentions that if
181 * we receive a SETUP phase instead of the DATA phase, core will issue
182 * XferComplete for the DATA phase, before actually initiating it in
183 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
184 * can only be used to print some debugging logs, as the core expects
185 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
186 * just so it completes right away, without transferring anything and,
187 * only then, we can go back to the SETUP phase.
188 *
189 * Because of this scenario, SNPS decided to change the programming
190 * model of control transfers and support on-demand transfers only for
191 * the STATUS phase. To fix the issue we have now, we will always wait
192 * for gadget driver to queue the DATA phase's struct usb_request, then
193 * start it right away.
194 *
195 * If we're actually in a 2-stage transfer, we will wait for
196 * XferNotReady(STATUS).
197 */
198 if (dwc->three_stage_setup) {
199 unsigned direction;
200
201 direction = dwc->ep0_expect_in;
202 dwc->ep0state = EP0_DATA_PHASE;
203
204 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
205
206 dep->flags &= ~DWC3_EP0_DIR_IN;
207 }
208
209 return 0;
210}
211
212int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
213 gfp_t gfp_flags)
214{
215 struct dwc3_request *req = to_dwc3_request(request);
216 struct dwc3_ep *dep = to_dwc3_ep(ep);
217 struct dwc3 *dwc = dep->dwc;
218
219 unsigned long flags;
220
221 int ret;
222
223 spin_lock_irqsave(&dwc->lock, flags);
224 if (!dep->endpoint.desc) {
225 dwc3_trace(trace_dwc3_ep0,
226 "trying to queue request %p to disabled %s",
227 request, dep->name);
228 ret = -ESHUTDOWN;
229 goto out;
230 }
231
232 /* we share one TRB for ep0/1 */
233 if (!list_empty(&dep->request_list)) {
234 ret = -EBUSY;
235 goto out;
236 }
237
238 dwc3_trace(trace_dwc3_ep0,
239 "queueing request %p to %s length %d state '%s'",
240 request, dep->name, request->length,
241 dwc3_ep0_state_string(dwc->ep0state));
242
243 ret = __dwc3_gadget_ep0_queue(dep, req);
244
245out:
246 spin_unlock_irqrestore(&dwc->lock, flags);
247
248 return ret;
249}
250
251static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
252{
253 struct dwc3_ep *dep;
254
255 /* reinitialize physical ep1 */
256 dep = dwc->eps[1];
257 dep->flags = DWC3_EP_ENABLED;
258
259 /* stall is always issued on EP0 */
260 dep = dwc->eps[0];
261 __dwc3_gadget_ep_set_halt(dep, 1, false);
262 dep->flags = DWC3_EP_ENABLED;
263 dwc->delayed_status = false;
264
265 if (!list_empty(&dep->request_list)) {
266 struct dwc3_request *req;
267
268 req = next_request(&dep->request_list);
269 dwc3_gadget_giveback(dep, req, -ECONNRESET);
270 }
271
272 dwc->ep0state = EP0_SETUP_PHASE;
273 dwc3_ep0_out_start(dwc);
274}
275
276int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
277{
278 struct dwc3_ep *dep = to_dwc3_ep(ep);
279 struct dwc3 *dwc = dep->dwc;
280
281 dwc3_ep0_stall_and_restart(dwc);
282
283 return 0;
284}
285
286int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
287{
288 struct dwc3_ep *dep = to_dwc3_ep(ep);
289 struct dwc3 *dwc = dep->dwc;
290 unsigned long flags;
291 int ret;
292
293 spin_lock_irqsave(&dwc->lock, flags);
294 ret = __dwc3_gadget_ep0_set_halt(ep, value);
295 spin_unlock_irqrestore(&dwc->lock, flags);
296
297 return ret;
298}
299
300void dwc3_ep0_out_start(struct dwc3 *dwc)
301{
302 int ret;
303
304 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
305 DWC3_TRBCTL_CONTROL_SETUP);
306 WARN_ON(ret < 0);
307}
308
309static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
310{
311 struct dwc3_ep *dep;
312 u32 windex = le16_to_cpu(wIndex_le);
313 u32 epnum;
314
315 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
316 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
317 epnum |= 1;
318
319 dep = dwc->eps[epnum];
320 if (dep->flags & DWC3_EP_ENABLED)
321 return dep;
322
323 return NULL;
324}
325
326static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
327{
328}
329/*
330 * ch 9.4.5
331 */
332static int dwc3_ep0_handle_status(struct dwc3 *dwc,
333 struct usb_ctrlrequest *ctrl)
334{
335 struct dwc3_ep *dep;
336 u32 recip;
337 u32 reg;
338 u16 usb_status = 0;
339 __le16 *response_pkt;
340
341 recip = ctrl->bRequestType & USB_RECIP_MASK;
342 switch (recip) {
343 case USB_RECIP_DEVICE:
344 /*
345 * LTM will be set once we know how to set this in HW.
346 */
347 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
348
349 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
350 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
351 if (reg & DWC3_DCTL_INITU1ENA)
352 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
353 if (reg & DWC3_DCTL_INITU2ENA)
354 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
355 }
356
357 break;
358
359 case USB_RECIP_INTERFACE:
360 /*
361 * Function Remote Wake Capable D0
362 * Function Remote Wakeup D1
363 */
364 break;
365
366 case USB_RECIP_ENDPOINT:
367 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
368 if (!dep)
369 return -EINVAL;
370
371 if (dep->flags & DWC3_EP_STALL)
372 usb_status = 1 << USB_ENDPOINT_HALT;
373 break;
374 default:
375 return -EINVAL;
376 }
377
378 response_pkt = (__le16 *) dwc->setup_buf;
379 *response_pkt = cpu_to_le16(usb_status);
380
381 dep = dwc->eps[0];
382 dwc->ep0_usb_req.dep = dep;
383 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
384 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
385 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
386
387 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
388}
389
390static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
391 struct usb_ctrlrequest *ctrl, int set)
392{
393 struct dwc3_ep *dep;
394 u32 recip;
395 u32 wValue;
396 u32 wIndex;
397 u32 reg;
398 int ret;
399 enum usb_device_state state;
400
401 wValue = le16_to_cpu(ctrl->wValue);
402 wIndex = le16_to_cpu(ctrl->wIndex);
403 recip = ctrl->bRequestType & USB_RECIP_MASK;
404 state = dwc->gadget.state;
405
406 switch (recip) {
407 case USB_RECIP_DEVICE:
408
409 switch (wValue) {
410 case USB_DEVICE_REMOTE_WAKEUP:
411 break;
412 /*
413 * 9.4.1 says only only for SS, in AddressState only for
414 * default control pipe
415 */
416 case USB_DEVICE_U1_ENABLE:
417 if (state != USB_STATE_CONFIGURED)
418 return -EINVAL;
419 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
420 return -EINVAL;
421
422 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
423 if (set)
424 reg |= DWC3_DCTL_INITU1ENA;
425 else
426 reg &= ~DWC3_DCTL_INITU1ENA;
427 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
428 break;
429
430 case USB_DEVICE_U2_ENABLE:
431 if (state != USB_STATE_CONFIGURED)
432 return -EINVAL;
433 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
434 return -EINVAL;
435
436 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
437 if (set)
438 reg |= DWC3_DCTL_INITU2ENA;
439 else
440 reg &= ~DWC3_DCTL_INITU2ENA;
441 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
442 break;
443
444 case USB_DEVICE_LTM_ENABLE:
445 return -EINVAL;
446
447 case USB_DEVICE_TEST_MODE:
448 if ((wIndex & 0xff) != 0)
449 return -EINVAL;
450 if (!set)
451 return -EINVAL;
452
453 dwc->test_mode_nr = wIndex >> 8;
454 dwc->test_mode = true;
455 break;
456 default:
457 return -EINVAL;
458 }
459 break;
460
461 case USB_RECIP_INTERFACE:
462 switch (wValue) {
463 case USB_INTRF_FUNC_SUSPEND:
464 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
465 /* XXX enable Low power suspend */
466 ;
467 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
468 /* XXX enable remote wakeup */
469 ;
470 break;
471 default:
472 return -EINVAL;
473 }
474 break;
475
476 case USB_RECIP_ENDPOINT:
477 switch (wValue) {
478 case USB_ENDPOINT_HALT:
479 dep = dwc3_wIndex_to_dep(dwc, wIndex);
480 if (!dep)
481 return -EINVAL;
482 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
483 break;
484 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
485 if (ret)
486 return -EINVAL;
487 break;
488 default:
489 return -EINVAL;
490 }
491 break;
492
493 default:
494 return -EINVAL;
495 }
496
497 return 0;
498}
499
500static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
501{
502 enum usb_device_state state = dwc->gadget.state;
503 u32 addr;
504 u32 reg;
505
506 addr = le16_to_cpu(ctrl->wValue);
507 if (addr > 127) {
508 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
509 return -EINVAL;
510 }
511
512 if (state == USB_STATE_CONFIGURED) {
513 dwc3_trace(trace_dwc3_ep0,
514 "trying to set address when configured");
515 return -EINVAL;
516 }
517
518 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
519 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
520 reg |= DWC3_DCFG_DEVADDR(addr);
521 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
522
523 if (addr)
524 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
525 else
526 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
527
528 return 0;
529}
530
531static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
532{
533 int ret;
534
535 spin_unlock(&dwc->lock);
536 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
537 spin_lock(&dwc->lock);
538 return ret;
539}
540
541static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
542{
543 enum usb_device_state state = dwc->gadget.state;
544 u32 cfg;
545 int ret;
546 u32 reg;
547
548 dwc->start_config_issued = false;
549 cfg = le16_to_cpu(ctrl->wValue);
550
551 switch (state) {
552 case USB_STATE_DEFAULT:
553 return -EINVAL;
554
555 case USB_STATE_ADDRESS:
556 ret = dwc3_ep0_delegate_req(dwc, ctrl);
557 /* if the cfg matches and the cfg is non zero */
558 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
559
560 /*
561 * only change state if set_config has already
562 * been processed. If gadget driver returns
563 * USB_GADGET_DELAYED_STATUS, we will wait
564 * to change the state on the next usb_ep_queue()
565 */
566 if (ret == 0)
567 usb_gadget_set_state(&dwc->gadget,
568 USB_STATE_CONFIGURED);
569
570 /*
571 * Enable transition to U1/U2 state when
572 * nothing is pending from application.
573 */
574 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
575 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
576 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
577
578 dwc->resize_fifos = true;
579 dwc3_trace(trace_dwc3_ep0, "resize FIFOs flag SET");
580 }
581 break;
582
583 case USB_STATE_CONFIGURED:
584 ret = dwc3_ep0_delegate_req(dwc, ctrl);
585 if (!cfg && !ret)
586 usb_gadget_set_state(&dwc->gadget,
587 USB_STATE_ADDRESS);
588 break;
589 default:
590 ret = -EINVAL;
591 }
592 return ret;
593}
594
595static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
596{
597 struct dwc3_ep *dep = to_dwc3_ep(ep);
598 struct dwc3 *dwc = dep->dwc;
599
600 u32 param = 0;
601 u32 reg;
602
603 struct timing {
604 u8 u1sel;
605 u8 u1pel;
606 u16 u2sel;
607 u16 u2pel;
608 } __packed timing;
609
610 int ret;
611
612 memcpy(&timing, req->buf, sizeof(timing));
613
614 dwc->u1sel = timing.u1sel;
615 dwc->u1pel = timing.u1pel;
616 dwc->u2sel = le16_to_cpu(timing.u2sel);
617 dwc->u2pel = le16_to_cpu(timing.u2pel);
618
619 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
620 if (reg & DWC3_DCTL_INITU2ENA)
621 param = dwc->u2pel;
622 if (reg & DWC3_DCTL_INITU1ENA)
623 param = dwc->u1pel;
624
625 /*
626 * According to Synopsys Databook, if parameter is
627 * greater than 125, a value of zero should be
628 * programmed in the register.
629 */
630 if (param > 125)
631 param = 0;
632
633 /* now that we have the time, issue DGCMD Set Sel */
634 ret = dwc3_send_gadget_generic_command(dwc,
635 DWC3_DGCMD_SET_PERIODIC_PAR, param);
636 WARN_ON(ret < 0);
637}
638
639static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
640{
641 struct dwc3_ep *dep;
642 enum usb_device_state state = dwc->gadget.state;
643 u16 wLength;
644 u16 wValue;
645
646 if (state == USB_STATE_DEFAULT)
647 return -EINVAL;
648
649 wValue = le16_to_cpu(ctrl->wValue);
650 wLength = le16_to_cpu(ctrl->wLength);
651
652 if (wLength != 6) {
653 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
654 wLength);
655 return -EINVAL;
656 }
657
658 /*
659 * To handle Set SEL we need to receive 6 bytes from Host. So let's
660 * queue a usb_request for 6 bytes.
661 *
662 * Remember, though, this controller can't handle non-wMaxPacketSize
663 * aligned transfers on the OUT direction, so we queue a request for
664 * wMaxPacketSize instead.
665 */
666 dep = dwc->eps[0];
667 dwc->ep0_usb_req.dep = dep;
668 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
669 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
670 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
671
672 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
673}
674
675static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
676{
677 u16 wLength;
678 u16 wValue;
679 u16 wIndex;
680
681 wValue = le16_to_cpu(ctrl->wValue);
682 wLength = le16_to_cpu(ctrl->wLength);
683 wIndex = le16_to_cpu(ctrl->wIndex);
684
685 if (wIndex || wLength)
686 return -EINVAL;
687
688 /*
689 * REVISIT It's unclear from Databook what to do with this
690 * value. For now, just cache it.
691 */
692 dwc->isoch_delay = wValue;
693
694 return 0;
695}
696
697static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
698{
699 int ret;
700
701 switch (ctrl->bRequest) {
702 case USB_REQ_GET_STATUS:
703 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS");
704 ret = dwc3_ep0_handle_status(dwc, ctrl);
705 break;
706 case USB_REQ_CLEAR_FEATURE:
707 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE");
708 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
709 break;
710 case USB_REQ_SET_FEATURE:
711 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE");
712 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
713 break;
714 case USB_REQ_SET_ADDRESS:
715 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS");
716 ret = dwc3_ep0_set_address(dwc, ctrl);
717 break;
718 case USB_REQ_SET_CONFIGURATION:
719 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION");
720 ret = dwc3_ep0_set_config(dwc, ctrl);
721 break;
722 case USB_REQ_SET_SEL:
723 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL");
724 ret = dwc3_ep0_set_sel(dwc, ctrl);
725 break;
726 case USB_REQ_SET_ISOCH_DELAY:
727 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY");
728 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
729 break;
730 default:
731 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver");
732 ret = dwc3_ep0_delegate_req(dwc, ctrl);
733 break;
734 }
735
736 return ret;
737}
738
739static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
740 const struct dwc3_event_depevt *event)
741{
742 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
743 int ret = -EINVAL;
744 u32 len;
745
746 if (!dwc->gadget_driver)
747 goto out;
748
749 trace_dwc3_ctrl_req(ctrl);
750
751 len = le16_to_cpu(ctrl->wLength);
752 if (!len) {
753 dwc->three_stage_setup = false;
754 dwc->ep0_expect_in = false;
755 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
756 } else {
757 dwc->three_stage_setup = true;
758 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
759 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
760 }
761
762 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
763 ret = dwc3_ep0_std_request(dwc, ctrl);
764 else
765 ret = dwc3_ep0_delegate_req(dwc, ctrl);
766
767 if (ret == USB_GADGET_DELAYED_STATUS)
768 dwc->delayed_status = true;
769
770out:
771 if (ret < 0)
772 dwc3_ep0_stall_and_restart(dwc);
773}
774
775static void dwc3_ep0_complete_data(struct dwc3 *dwc,
776 const struct dwc3_event_depevt *event)
777{
778 struct dwc3_request *r = NULL;
779 struct usb_request *ur;
780 struct dwc3_trb *trb;
781 struct dwc3_ep *ep0;
782 u32 transferred;
783 u32 status;
784 u32 length;
785 u8 epnum;
786
787 epnum = event->endpoint_number;
788 ep0 = dwc->eps[0];
789
790 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
791
792 trb = dwc->ep0_trb;
793
794 trace_dwc3_complete_trb(ep0, trb);
795
796 r = next_request(&ep0->request_list);
797 if (!r)
798 return;
799
800 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
801 if (status == DWC3_TRBSTS_SETUP_PENDING) {
802 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
803
804 if (r)
805 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
806
807 return;
808 }
809
810 ur = &r->request;
811
812 length = trb->size & DWC3_TRB_SIZE_MASK;
813
814 if (dwc->ep0_bounced) {
815 unsigned transfer_size = ur->length;
816 unsigned maxp = ep0->endpoint.maxpacket;
817
818 transfer_size += (maxp - (transfer_size % maxp));
819 transferred = min_t(u32, ur->length,
820 transfer_size - length);
821 memcpy(ur->buf, dwc->ep0_bounce, transferred);
822 } else {
823 transferred = ur->length - length;
824 }
825
826 ur->actual += transferred;
827
828 if ((epnum & 1) && ur->actual < ur->length) {
829 /* for some reason we did not get everything out */
830
831 dwc3_ep0_stall_and_restart(dwc);
832 } else {
833 dwc3_gadget_giveback(ep0, r, 0);
834
835 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
836 ur->length && ur->zero) {
837 int ret;
838
839 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
840
841 ret = dwc3_ep0_start_trans(dwc, epnum,
842 dwc->ctrl_req_addr, 0,
843 DWC3_TRBCTL_CONTROL_DATA);
844 WARN_ON(ret < 0);
845 }
846 }
847}
848
849static void dwc3_ep0_complete_status(struct dwc3 *dwc,
850 const struct dwc3_event_depevt *event)
851{
852 struct dwc3_request *r;
853 struct dwc3_ep *dep;
854 struct dwc3_trb *trb;
855 u32 status;
856
857 dep = dwc->eps[0];
858 trb = dwc->ep0_trb;
859
860 trace_dwc3_complete_trb(dep, trb);
861
862 if (!list_empty(&dep->request_list)) {
863 r = next_request(&dep->request_list);
864
865 dwc3_gadget_giveback(dep, r, 0);
866 }
867
868 if (dwc->test_mode) {
869 int ret;
870
871 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
872 if (ret < 0) {
873 dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
874 dwc->test_mode_nr);
875 dwc3_ep0_stall_and_restart(dwc);
876 return;
877 }
878 }
879
880 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
881 if (status == DWC3_TRBSTS_SETUP_PENDING)
882 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
883
884 dwc->ep0state = EP0_SETUP_PHASE;
885 dwc3_ep0_out_start(dwc);
886}
887
888static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
889 const struct dwc3_event_depevt *event)
890{
891 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
892
893 dep->flags &= ~DWC3_EP_BUSY;
894 dep->resource_index = 0;
895 dwc->setup_packet_pending = false;
896
897 switch (dwc->ep0state) {
898 case EP0_SETUP_PHASE:
899 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
900 dwc3_ep0_inspect_setup(dwc, event);
901 break;
902
903 case EP0_DATA_PHASE:
904 dwc3_trace(trace_dwc3_ep0, "Data Phase");
905 dwc3_ep0_complete_data(dwc, event);
906 break;
907
908 case EP0_STATUS_PHASE:
909 dwc3_trace(trace_dwc3_ep0, "Status Phase");
910 dwc3_ep0_complete_status(dwc, event);
911 break;
912 default:
913 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
914 }
915}
916
917static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
918 struct dwc3_ep *dep, struct dwc3_request *req)
919{
920 int ret;
921
922 req->direction = !!dep->number;
923
924 if (req->request.length == 0) {
925 ret = dwc3_ep0_start_trans(dwc, dep->number,
926 dwc->ctrl_req_addr, 0,
927 DWC3_TRBCTL_CONTROL_DATA);
928 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
929 && (dep->number == 0)) {
930 u32 transfer_size;
931 u32 maxpacket;
932
933 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
934 dep->number);
935 if (ret) {
936 dev_dbg(dwc->dev, "failed to map request\n");
937 return;
938 }
939
940 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE);
941
942 maxpacket = dep->endpoint.maxpacket;
943 transfer_size = roundup(req->request.length, maxpacket);
944
945 dwc->ep0_bounced = true;
946
947 /*
948 * REVISIT in case request length is bigger than
949 * DWC3_EP0_BOUNCE_SIZE we will need two chained
950 * TRBs to handle the transfer.
951 */
952 ret = dwc3_ep0_start_trans(dwc, dep->number,
953 dwc->ep0_bounce_addr, transfer_size,
954 DWC3_TRBCTL_CONTROL_DATA);
955 } else {
956 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
957 dep->number);
958 if (ret) {
959 dev_dbg(dwc->dev, "failed to map request\n");
960 return;
961 }
962
963 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
964 req->request.length, DWC3_TRBCTL_CONTROL_DATA);
965 }
966
967 WARN_ON(ret < 0);
968}
969
970static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
971{
972 struct dwc3 *dwc = dep->dwc;
973 u32 type;
974
975 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
976 : DWC3_TRBCTL_CONTROL_STATUS2;
977
978 return dwc3_ep0_start_trans(dwc, dep->number,
979 dwc->ctrl_req_addr, 0, type);
980}
981
982static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
983{
984 if (dwc->resize_fifos) {
985 dwc3_trace(trace_dwc3_ep0, "Resizing FIFOs");
986 dwc3_gadget_resize_tx_fifos(dwc);
987 dwc->resize_fifos = 0;
988 }
989
990 WARN_ON(dwc3_ep0_start_control_status(dep));
991}
992
993static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
994 const struct dwc3_event_depevt *event)
995{
996 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
997
998 __dwc3_ep0_do_control_status(dwc, dep);
999}
1000
1001static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1002{
1003 struct dwc3_gadget_ep_cmd_params params;
1004 u32 cmd;
1005 int ret;
1006
1007 if (!dep->resource_index)
1008 return;
1009
1010 cmd = DWC3_DEPCMD_ENDTRANSFER;
1011 cmd |= DWC3_DEPCMD_CMDIOC;
1012 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1013 memset(&params, 0, sizeof(params));
1014 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1015 WARN_ON_ONCE(ret);
1016 dep->resource_index = 0;
1017}
1018
1019static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1020 const struct dwc3_event_depevt *event)
1021{
1022 dwc->setup_packet_pending = true;
1023
1024 switch (event->status) {
1025 case DEPEVT_STATUS_CONTROL_DATA:
1026 dwc3_trace(trace_dwc3_ep0, "Control Data");
1027
1028 /*
1029 * We already have a DATA transfer in the controller's cache,
1030 * if we receive a XferNotReady(DATA) we will ignore it, unless
1031 * it's for the wrong direction.
1032 *
1033 * In that case, we must issue END_TRANSFER command to the Data
1034 * Phase we already have started and issue SetStall on the
1035 * control endpoint.
1036 */
1037 if (dwc->ep0_expect_in != event->endpoint_number) {
1038 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1039
1040 dwc3_trace(trace_dwc3_ep0,
1041 "Wrong direction for Data phase");
1042 dwc3_ep0_end_control_data(dwc, dep);
1043 dwc3_ep0_stall_and_restart(dwc);
1044 return;
1045 }
1046
1047 break;
1048
1049 case DEPEVT_STATUS_CONTROL_STATUS:
1050 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1051 return;
1052
1053 dwc3_trace(trace_dwc3_ep0, "Control Status");
1054
1055 dwc->ep0state = EP0_STATUS_PHASE;
1056
1057 if (dwc->delayed_status) {
1058 WARN_ON_ONCE(event->endpoint_number != 1);
1059 dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1060 return;
1061 }
1062
1063 dwc3_ep0_do_control_status(dwc, event);
1064 }
1065}
1066
1067void dwc3_ep0_interrupt(struct dwc3 *dwc,
1068 const struct dwc3_event_depevt *event)
1069{
1070 u8 epnum = event->endpoint_number;
1071
1072 dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'",
1073 dwc3_ep_event_string(event->endpoint_event),
1074 epnum >> 1, (epnum & 1) ? "in" : "out",
1075 dwc3_ep0_state_string(dwc->ep0state));
1076
1077 switch (event->endpoint_event) {
1078 case DWC3_DEPEVT_XFERCOMPLETE:
1079 dwc3_ep0_xfer_complete(dwc, event);
1080 break;
1081
1082 case DWC3_DEPEVT_XFERNOTREADY:
1083 dwc3_ep0_xfernotready(dwc, event);
1084 break;
1085
1086 case DWC3_DEPEVT_XFERINPROGRESS:
1087 case DWC3_DEPEVT_RXTXFIFOEVT:
1088 case DWC3_DEPEVT_STREAMEVT:
1089 case DWC3_DEPEVT_EPCMDCMPLT:
1090 break;
1091 }
1092}