Martyn Welch | 0963060 | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2018 Collabora Ltd. |
| 4 | * |
| 5 | * Based on include/configs/xpress.h: |
| 6 | * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> |
| 7 | */ |
| 8 | #ifndef __PCL063_H |
| 9 | #define __PCL063_H |
| 10 | |
| 11 | #include <linux/sizes.h> |
| 12 | #include "mx6_common.h" |
| 13 | |
| 14 | /* SPL options */ |
| 15 | #include "imx6_spl.h" |
| 16 | |
| 17 | /* |
| 18 | * There is a bug in some i.MX6UL processors that results in the initial |
| 19 | * portion of OCRAM being unavailable when booting from (at least) an SD |
| 20 | * card. |
| 21 | * |
| 22 | * Tweak the SPL text base address to avoid this. |
| 23 | */ |
Martyn Welch | 0963060 | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 24 | |
Tom Rini | 6cc0454 | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 25 | #define CFG_SYS_FSL_USDHC_NUM 1 |
Parthiban Nallathambi | d2d1191 | 2019-04-10 16:35:32 +0200 | [diff] [blame] | 26 | |
Martyn Welch | 0963060 | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 27 | /* Console configs */ |
| 28 | #define CONFIG_MXC_UART_BASE UART1_BASE |
| 29 | |
| 30 | /* MMC Configs */ |
Martyn Welch | 0963060 | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 31 | |
Tom Rini | 6cc0454 | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 32 | #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR |
Martyn Welch | 0963060 | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 33 | |
| 34 | /* Miscellaneous configurable options */ |
Martyn Welch | 0963060 | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 35 | |
Martyn Welch | 0963060 | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 36 | /* Physical Memory Map */ |
| 37 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
| 38 | #define PHYS_SDRAM_SIZE SZ_256M |
| 39 | |
| 40 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
| 41 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
| 42 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
| 43 | |
Martyn Welch | 0963060 | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 44 | /* NAND */ |
Tom Rini | 84d8c38 | 2022-11-12 13:19:56 -0500 | [diff] [blame^] | 45 | #define CFG_SYS_NAND_BASE 0x40000000 |
Martyn Welch | 0963060 | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 46 | |
| 47 | /* USB Configs */ |
Martyn Welch | 0963060 | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 48 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
| 49 | #define CONFIG_MXC_USB_FLAGS 0 |
Martyn Welch | 0963060 | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 50 | |
Martyn Welch | 0963060 | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 51 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 52 | "console=ttymxc0,115200n8\0" \ |
Martyn Welch | 0963060 | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 53 | "fdt_addr_r=0x82000000\0" \ |
| 54 | "fdt_high=0xffffffff\0" \ |
| 55 | "initrd_high=0xffffffff\0" \ |
| 56 | "kernel_addr_r=0x81000000\0" \ |
| 57 | "pxefile_addr_r=0x87100000\0" \ |
| 58 | "ramdisk_addr_r=0x82100000\0" \ |
| 59 | "scriptaddr=0x87000000\0" \ |
| 60 | BOOTENV |
| 61 | |
| 62 | #define BOOT_TARGET_DEVICES(func) \ |
| 63 | func(MMC, mmc, 0) \ |
Pali Rohár | e6ca148 | 2022-05-31 10:32:36 +0200 | [diff] [blame] | 64 | func(UBIFS, ubifs, 0, UBI, boot) \ |
Martyn Welch | 0963060 | 2018-12-11 11:34:46 +0000 | [diff] [blame] | 65 | func(PXE, pxe, na) \ |
| 66 | func(DHCP, dhcp, na) |
| 67 | |
| 68 | #include <config_distro_bootcmd.h> |
| 69 | |
| 70 | #endif /* __PCL063_H */ |