blob: 02150bafdc0f5f7df94436dd47df8cac6ee990a1 [file] [log] [blame]
Anton Vorontsovfd6646c2009-01-08 04:26:12 +03001/*
2 * Copyright (C) 2007-2009 Freescale Semiconductor, Inc.
3 * Copyright (C) 2008-2009 MontaVista Software, Inc.
4 *
5 * Authors: Tony Li <tony.li@freescale.com>
6 * Anton Vorontsov <avorontsov@ru.mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <pci.h>
26#include <mpc83xx.h>
27#include <asm/io.h>
28
29DECLARE_GLOBAL_DATA_PTR;
30
31#define PCIE_MAX_BUSES 2
32
33#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
34
35static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
36{
37 int bus = PCI_BUS(dev) - hose->first_busno;
38 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
39 pex83xx_t *pex = &immr->pciexp[bus];
40 struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
41 u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
42 u32 dev_base = bus << 24 | devfn << 16;
43
44 if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK)
45 return -1;
46 /*
47 * Workaround for the HW bug: for Type 0 configure transactions the
48 * PCI-E controller does not check the device number bits and just
49 * assumes that the device number bits are 0.
50 */
51 if (devfn & 0xf8)
52 return -1;
53
54 out_le32(&out_win->tarl, dev_base);
55 return 0;
56}
57
58#define cfg_read(val, addr, type, op) \
59 do { *val = op((type)(addr)); } while (0)
60#define cfg_write(val, addr, type, op) \
61 do { op((type *)(addr), (val)); } while (0)
62
63#define PCIE_OP(rw, size, type, op) \
64static int pcie_##rw##_config_##size(struct pci_controller *hose, \
65 pci_dev_t dev, int offset, \
66 type val) \
67{ \
68 int ret; \
69 \
70 ret = mpc83xx_pcie_remap_cfg(hose, dev); \
71 if (ret) \
72 return ret; \
73 cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \
74 return 0; \
75}
76
77PCIE_OP(read, byte, u8 *, in_8)
78PCIE_OP(read, word, u16 *, in_le16)
79PCIE_OP(read, dword, u32 *, in_le32)
80PCIE_OP(write, byte, u8, out_8)
81PCIE_OP(write, word, u16, out_le16)
82PCIE_OP(write, dword, u32, out_le32)
83
84static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
85 u8 link)
86{
87 extern void disable_addr_trans(void); /* start.S */
88 static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
89 static int max_bus;
90 struct pci_controller *hose = &pcie_hose[bus];
91 int i;
92
93 /*
94 * There are no spare BATs to remap all PCI-E windows for U-Boot, so
95 * disable translations. In general, this is not great solution, and
96 * that's why we don't register PCI-E hoses by default.
97 */
98 disable_addr_trans();
99
100 for (i = 0; i < 2; i++, reg++) {
101 if (reg->size == 0)
102 break;
103
104 hose->regions[i] = *reg;
105 hose->region_count++;
106 }
107
108 i = hose->region_count++;
109 hose->regions[i].bus_start = 0;
110 hose->regions[i].phys_start = 0;
111 hose->regions[i].size = gd->ram_size;
112 hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
113
114 i = hose->region_count++;
115 hose->regions[i].bus_start = CONFIG_SYS_IMMR;
116 hose->regions[i].phys_start = CONFIG_SYS_IMMR;
117 hose->regions[i].size = 0x100000;
118 hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
119
120 hose->first_busno = max_bus;
121 hose->last_busno = 0xff;
122
123 if (bus == 0)
124 hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE1_CFG_BASE;
125 else
126 hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE2_CFG_BASE;
127
128 pci_set_ops(hose,
129 pcie_read_config_byte,
130 pcie_read_config_word,
131 pcie_read_config_dword,
132 pcie_write_config_byte,
133 pcie_write_config_word,
134 pcie_write_config_dword);
135
136 if (!link)
137 hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK;
138
139 pci_register_hose(hose);
140
141#ifdef CONFIG_PCI_SCAN_SHOW
142 printf("PCI: Bus Dev VenId DevId Class Int\n");
143#endif
144 /*
145 * Hose scan.
146 */
147 hose->last_busno = pci_hose_scan(hose);
148 max_bus = hose->last_busno + 1;
149}
150
151#else
152
153static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
154 u8 link) {}
155
156#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
157
158static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
159{
160 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
161 pex83xx_t *pex = &immr->pciexp[bus];
162 struct pex_outbound_window *out_win;
163 struct pex_inbound_window *in_win;
164 void *hose_cfg_base;
165 unsigned int ram_sz;
166 unsigned int barl;
167 unsigned int tar;
168 u16 reg16;
169 int i;
170
171 /* Enable pex csb bridge inbound & outbound transactions */
172 out_le32(&pex->bridge.pex_csb_ctrl,
173 in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE |
174 PEX_CSB_CTRL_IBPIOE);
175
176 /* Enable bridge outbound */
177 out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE |
178 PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE |
179 PEX_CSB_OBCTRL_CFGWE);
180
181 out_win = &pex->bridge.pex_outbound_win[0];
182 if (bus) {
183 out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
184 CONFIG_SYS_PCIE2_CFG_SIZE);
185 out_le32(&out_win->bar, CONFIG_SYS_PCIE2_CFG_BASE);
186 } else {
187 out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
188 CONFIG_SYS_PCIE1_CFG_SIZE);
189 out_le32(&out_win->bar, CONFIG_SYS_PCIE1_CFG_BASE);
190 }
191 out_le32(&out_win->tarl, 0);
192 out_le32(&out_win->tarh, 0);
193
194 for (i = 0; i < 2; i++, reg++) {
195 u32 ar;
196
197 if (reg->size == 0)
198 break;
199
200 out_win = &pex->bridge.pex_outbound_win[i + 1];
201 out_le32(&out_win->bar, reg->phys_start);
202 out_le32(&out_win->tarl, reg->bus_start);
203 out_le32(&out_win->tarh, 0);
204 ar = PEX_OWAR_EN | (reg->size & PEX_OWAR_SIZE);
205 if (reg->flags & PCI_REGION_IO)
206 ar |= PEX_OWAR_TYPE_IO;
207 else
208 ar |= PEX_OWAR_TYPE_MEM;
209 out_le32(&out_win->ar, ar);
210 }
211
212 out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE);
213
214 ram_sz = gd->ram_size;
215 barl = 0;
216 tar = 0;
217 i = 0;
218 while (ram_sz > 0) {
219 in_win = &pex->bridge.pex_inbound_win[i];
220 out_le32(&in_win->barl, barl);
221 out_le32(&in_win->barh, 0x0);
222 out_le32(&in_win->tar, tar);
223 if (ram_sz >= 0x10000000) {
224 /* The maxium windows size is 256M */
225 out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
226 PEX_IWAR_TYPE_PF | 0x0FFFF000);
227 barl += 0x10000000;
228 tar += 0x10000000;
229 ram_sz -= 0x10000000;
230 } else {
231 /* The UM is not clear here.
232 * So, round up to even Mb boundary */
233
234 ram_sz = ram_sz >> (20 +
235 ((ram_sz & 0xFFFFF) ? 1 : 0));
236 if (!(ram_sz % 2))
237 ram_sz -= 1;
238 out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
239 PEX_IWAR_TYPE_PF | (ram_sz << 20) | 0xFF000);
240 ram_sz = 0;
241 }
242 i++;
243 }
244
245 in_win = &pex->bridge.pex_inbound_win[i];
246 out_le32(&in_win->barl, CONFIG_SYS_IMMR);
247 out_le32(&in_win->barh, 0);
248 out_le32(&in_win->tar, CONFIG_SYS_IMMR);
249 out_le32(&in_win->ar, PEX_IWAR_EN |
250 PEX_IWAR_TYPE_NO_PF | PEX_IWAR_SIZE_1M);
251
252 /* Enable the host virtual INTX interrupts */
253 out_le32(&pex->bridge.pex_int_axi_misc_enb,
254 in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0);
255
256 /* Hose configure header is memory-mapped */
257 hose_cfg_base = (void *)pex;
258
259 get_clocks();
260 /* Configure the PCIE controller core clock ratio */
261 out_le32(hose_cfg_base + PEX_GCLK_RATIO,
262 (((bus ? gd->pciexp2_clk : gd->pciexp1_clk) / 1000000) * 16)
263 / 333);
264 udelay(1000000);
265
266 /* Do Type 1 bridge configuration */
267 out_8(hose_cfg_base + PCI_PRIMARY_BUS, 0);
268 out_8(hose_cfg_base + PCI_SECONDARY_BUS, 1);
269 out_8(hose_cfg_base + PCI_SUBORDINATE_BUS, 255);
270
271 /*
272 * Write to Command register
273 */
274 reg16 = in_le16(hose_cfg_base + PCI_COMMAND);
275 reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO |
276 PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
277 out_le16(hose_cfg_base + PCI_COMMAND, reg16);
278
279 /*
280 * Clear non-reserved bits in status register.
281 */
282 out_le16(hose_cfg_base + PCI_STATUS, 0xffff);
283 out_8(hose_cfg_base + PCI_LATENCY_TIMER, 0x80);
284 out_8(hose_cfg_base + PCI_CACHE_LINE_SIZE, 0x08);
285
286 printf("PCIE%d: ", bus);
287
288 reg16 = in_le16(hose_cfg_base + PCI_LTSSM);
289 if (reg16 >= PCI_LTSSM_L0)
290 printf("link\n");
291 else
292 printf("No link\n");
293
294 mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0);
295}
296
297/*
298 * The caller must have already set SCCR, SERDES and the PCIE_LAW BARs
299 * must have been set to cover all of the requested regions.
300 */
301void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot)
302{
303 int i;
304
305 /*
306 * Release PCI RST Output signal.
307 * Power on to RST high must be at least 100 ms as per PCI spec.
308 * On warm boots only 1 ms is required.
309 */
310 udelay(warmboot ? 1000 : 100000);
311
312 for (i = 0; i < num_buses; i++)
313 mpc83xx_pcie_init_bus(i, reg[i]);
314}