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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenkc6097192002-11-03 00:24:07 +00002/*
3 * (C) Copyright 2002
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenkc6097192002-11-03 00:24:07 +00005 */
6
7#include <fpga.h>
8
9#ifndef _XILINX_H_
10#define _XILINX_H_
11
wdenkc6097192002-11-03 00:24:07 +000012/* Xilinx types
13 *********************************************************************/
Michal Simek2df9d5c2014-03-13 12:58:20 +010014typedef enum { /* typedef xilinx_iface */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020015 min_xilinx_iface_type, /* low range check value */
16 slave_serial, /* serial data and external clock */
17 master_serial, /* serial data w/ internal clock (not used) */
18 slave_parallel, /* parallel data w/ external latch */
19 jtag_mode, /* jtag/tap serial (not used ) */
20 master_selectmap, /* master SelectMap (virtex2) */
21 slave_selectmap, /* slave SelectMap (virtex2) */
Michal Simekd5dae852013-04-22 15:43:02 +020022 devcfg, /* devcfg interface (zynq) */
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +053023 csu_dma, /* csu_dma interface (zynqmp) */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020024 max_xilinx_iface_type /* insert all new types before this */
Michal Simek2df9d5c2014-03-13 12:58:20 +010025} xilinx_iface; /* end, typedef xilinx_iface */
wdenkc6097192002-11-03 00:24:07 +000026
Michal Simek2df9d5c2014-03-13 12:58:20 +010027typedef enum { /* typedef xilinx_family */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020028 min_xilinx_type, /* low range check value */
Michal Simekb625b9a2014-03-13 11:23:43 +010029 xilinx_spartan2, /* Spartan-II Family */
Michal Simek2df9d5c2014-03-13 12:58:20 +010030 xilinx_virtexE, /* Virtex-E Family */
Michal Simekd9071ce2014-03-13 11:33:36 +010031 xilinx_virtex2, /* Virtex2 Family */
Michal Simek2a6e3862014-03-13 11:28:42 +010032 xilinx_spartan3, /* Spartan-III Family */
Michal Simekd5dae852013-04-22 15:43:02 +020033 xilinx_zynq, /* Zynq Family */
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +053034 xilinx_zynqmp, /* ZynqMP Family */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020035 max_xilinx_type /* insert all new types before this */
Michal Simek2df9d5c2014-03-13 12:58:20 +010036} xilinx_family; /* end, typedef xilinx_family */
wdenkc6097192002-11-03 00:24:07 +000037
Michal Simekf8c1be92014-03-13 12:49:21 +010038typedef struct { /* typedef xilinx_desc */
Michal Simek2df9d5c2014-03-13 12:58:20 +010039 xilinx_family family; /* part type */
40 xilinx_iface iface; /* interface type */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020041 size_t size; /* bytes of data part can accept */
42 void *iface_fns; /* interface function table */
43 int cookie; /* implementation specific cookie */
Michal Simek14cfc4f2014-03-13 13:07:57 +010044 struct xilinx_fpga_op *operations; /* operations */
Michal Simek6631db42013-04-26 15:04:48 +020045 char *name; /* device name in bitstream */
Michal Simekf8c1be92014-03-13 12:49:21 +010046} xilinx_desc; /* end, typedef xilinx_desc */
wdenkc6097192002-11-03 00:24:07 +000047
Michal Simek14cfc4f2014-03-13 13:07:57 +010048struct xilinx_fpga_op {
Michal Simek7a78bd22014-05-02 14:09:30 +020049 int (*load)(xilinx_desc *, const void *, size_t, bitstream_type);
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053050 int (*loadfs)(xilinx_desc *, const void *, size_t, fpga_fs_info *);
Michal Simek14cfc4f2014-03-13 13:07:57 +010051 int (*dump)(xilinx_desc *, const void *, size_t);
52 int (*info)(xilinx_desc *);
53};
54
wdenkc6097192002-11-03 00:24:07 +000055/* Generic Xilinx Functions
56 *********************************************************************/
Michal Simek7a78bd22014-05-02 14:09:30 +020057int xilinx_load(xilinx_desc *desc, const void *image, size_t size,
58 bitstream_type bstype);
Michal Simekf8c1be92014-03-13 12:49:21 +010059int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize);
60int xilinx_info(xilinx_desc *desc);
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053061int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
62 fpga_fs_info *fpga_fsinfo);
wdenkc6097192002-11-03 00:24:07 +000063
64/* Board specific implementation specific function types
65 *********************************************************************/
Michal Simek2df9d5c2014-03-13 12:58:20 +010066typedef int (*xilinx_pgm_fn)(int assert_pgm, int flush, int cookie);
67typedef int (*xilinx_init_fn)(int cookie);
68typedef int (*xilinx_err_fn)(int cookie);
69typedef int (*xilinx_done_fn)(int cookie);
70typedef int (*xilinx_clk_fn)(int assert_clk, int flush, int cookie);
71typedef int (*xilinx_cs_fn)(int assert_cs, int flush, int cookie);
72typedef int (*xilinx_wr_fn)(int assert_write, int flush, int cookie);
73typedef int (*xilinx_rdata_fn)(unsigned char *data, int cookie);
74typedef int (*xilinx_wdata_fn)(unsigned char data, int flush, int cookie);
75typedef int (*xilinx_busy_fn)(int cookie);
76typedef int (*xilinx_abort_fn)(int cookie);
77typedef int (*xilinx_pre_fn)(int cookie);
78typedef int (*xilinx_post_fn)(int cookie);
79typedef int (*xilinx_bwr_fn)(void *buf, size_t len, int flush, int cookie);
wdenkc6097192002-11-03 00:24:07 +000080
81#endif /* _XILINX_H_ */