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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Dirk Eibach60083262017-02-22 16:07:23 +01002/*
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
Dirk Eibach60083262017-02-22 16:07:23 +01005 */
6
7#ifndef _CONFIG_CONTROLCENTERDC_H
8#define _CONFIG_CONTROLCENTERDC_H
9
10/*
11 * High Level Configuration Options (easy to change)
12 */
13#define CONFIG_CUSTOMER_BOARD_SUPPORT
14
15#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
Dirk Eibach60083262017-02-22 16:07:23 +010016#define CONFIG_BOARD_LATE_INIT
Dirk Eibach60083262017-02-22 16:07:23 +010017
18/*
19 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
20 * for DDR ECC byte filling in the SPL before loading the main
21 * U-Boot into it.
22 */
Dirk Eibach60083262017-02-22 16:07:23 +010023
24#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
25
26#define CONFIG_LOADADDR 1000000
27
28/*
29 * Commands configuration
30 */
Dirk Eibach60083262017-02-22 16:07:23 +010031#define CONFIG_CMD_I2C
Dirk Eibach60083262017-02-22 16:07:23 +010032#define CONFIG_CMD_SPI
33
34/* SPI NOR flash default params, used by sf commands */
35#define CONFIG_SF_DEFAULT_BUS 1
36#define CONFIG_SF_DEFAULT_SPEED 1000000
37#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
38
39/*
40 * SDIO/MMC Card Configuration
41 */
42#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
43
44/*
45 * SATA/SCSI/AHCI configuration
46 */
Dirk Eibach60083262017-02-22 16:07:23 +010047#define CONFIG_SCSI_AHCI_PLAT
48#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
49#define CONFIG_SYS_SCSI_MAX_LUN 1
50#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
51 CONFIG_SYS_SCSI_MAX_LUN)
52
Dirk Eibach60083262017-02-22 16:07:23 +010053/* USB/EHCI configuration */
54#define CONFIG_EHCI_IS_TDI
55
56/* Environment in SPI NOR flash */
Dirk Eibach60083262017-02-22 16:07:23 +010057#define CONFIG_ENV_SPI_BUS 1
58#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
59#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
60#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
61
62#define CONFIG_PHY_MARVELL /* there is a marvell phy */
63#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
64
65/* PCIe support */
66#ifndef CONFIG_SPL_BUILD
67#define CONFIG_PCI
68#define CONFIG_PCI_MVEBU
69#define CONFIG_PCI_PNP
70#define CONFIG_PCI_SCAN_SHOW
71#endif
72
Dirk Eibach60083262017-02-22 16:07:23 +010073/*
74 * Software (bit-bang) MII driver configuration
75 */
76#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
77#define CONFIG_BITBANGMII_MULTI
78
79/* SPL */
80/*
81 * Select the boot device here
82 *
83 * Currently supported are:
84 * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
85 * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
86 */
87#define SPL_BOOT_SPI_NOR_FLASH 1
88#define SPL_BOOT_SDIO_MMC_CARD 2
89#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
90
91/* Defines for SPL */
Dirk Eibach60083262017-02-22 16:07:23 +010092#define CONFIG_SPL_SIZE (160 << 10)
93
94#if defined(CONFIG_SECURED_MODE_IMAGE)
95#define CONFIG_SPL_TEXT_BASE 0x40002614
96#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x2614)
97#else
98#define CONFIG_SPL_TEXT_BASE 0x40000030
99#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x30)
100#endif
101
102#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
103#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
104
105#ifdef CONFIG_SPL_BUILD
106#define CONFIG_SYS_MALLOC_SIMPLE
107#endif
108
109#define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10))
110#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
111
112#define CONFIG_SPL_LIBCOMMON_SUPPORT
113#define CONFIG_SPL_LIBGENERIC_SUPPORT
Dirk Eibach60083262017-02-22 16:07:23 +0100114#define CONFIG_SPL_I2C_SUPPORT
115
116#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
117/* SPL related SPI defines */
Dirk Eibach60083262017-02-22 16:07:23 +0100118#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000
119#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
120#endif
121
122#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
123/* SPL related MMC defines */
124#define CONFIG_SPL_MMC_SUPPORT
125#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
126#define CONFIG_SYS_MMC_U_BOOT_OFFS (168 << 10)
127#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
128#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512)
129#ifdef CONFIG_SPL_BUILD
130#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
131#endif
132#endif
133
134/*
135 * Environment Configuration
136 */
137#define CONFIG_ENV_OVERWRITE
138
139#define CONFIG_BAUDRATE 115200
140
Mario Six5bc05432018-03-28 14:38:20 +0200141#define CONFIG_HOSTNAME "ccdc"
Dirk Eibach60083262017-02-22 16:07:23 +0100142#define CONFIG_ROOTPATH "/opt/nfsroot"
143#define CONFIG_BOOTFILE "ccdc.img"
144
145#define CONFIG_PREBOOT /* enable preboot variable */
146
147#define CONFIG_EXTRA_ENV_SETTINGS \
148 "netdev=eth1\0" \
149 "consoledev=ttyS1\0" \
150 "u-boot=u-boot.bin\0" \
151 "bootfile_addr=1000000\0" \
152 "keyprogram_addr=3000000\0" \
153 "keyprogram_file=keyprogram.img\0" \
154 "fdtfile=controlcenterdc.dtb\0" \
155 "load=tftpboot ${loadaddr} ${u-boot}\0" \
156 "mmcdev=0:2\0" \
157 "update=sf probe 1:0;" \
158 " sf erase 0 +${filesize};" \
159 " sf write ${fileaddr} 0 ${filesize}\0" \
160 "upd=run load update\0" \
161 "fdt_high=0x10000000\0" \
162 "initrd_high=0x10000000\0" \
163 "loadkeyprogram=tpm flush_keys;" \
164 " mmc rescan;" \
165 " ext4load mmc ${mmcdev} ${keyprogram_addr} ${keyprogram_file};"\
166 " source ${keyprogram_addr}:script@1\0" \
167 "gpio1=gpio@22_25\0" \
168 "gpio2=A29\0" \
169 "blinkseq='0 0 0 0 2 0 2 2 3 1 3 1 0 0 2 2 3 1 3 3 2 0 2 2 3 1 1 1 " \
170 "2 0 2 2 3 1 3 1 0 0 2 0 3 3 3 1 2 0 0 0 3 1 1 1 0 0 0 0'\0" \
171 "bootfail=for i in ${blinkseq}; do" \
172 " if test $i -eq 0; then" \
173 " gpio clear ${gpio1}; gpio set ${gpio2};" \
174 " elif test $i -eq 1; then" \
175 " gpio clear ${gpio1}; gpio clear ${gpio2};" \
176 " elif test $i -eq 2; then" \
177 " gpio set ${gpio1}; gpio set ${gpio2};" \
178 " else;" \
179 " gpio clear ${gpio1}; gpio set ${gpio2};" \
180 " fi; sleep 0.12; done\0"
181
182#define CONFIG_NFSBOOTCOMMAND \
183 "setenv bootargs root=/dev/nfs rw " \
184 "nfsroot=${serverip}:${rootpath} " \
185 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off " \
186 "console=${consoledev},${baudrate} ${othbootargs}; " \
187 "tftpboot ${bootfile_addr} ${bootfile}; " \
188 "bootm ${bootfile_addr}"
189
190#define CONFIG_MMCBOOTCOMMAND \
191 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
192 "console=${consoledev},${baudrate} ${othbootargs}; " \
193 "ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; " \
194 "bootm ${bootfile_addr}"
195
196#define CONFIG_BOOTCOMMAND \
197 "if env exists keyprogram; then;" \
198 " setenv keyprogram; run nfsboot;" \
199 " fi;" \
200 " run dobootfail"
201
202/*
203 * mv-common.h should be defined after CMD configs since it used them
204 * to enable certain macros
205 */
206#include "mv-common.h"
207
208#endif /* _CONFIG_CONTROLCENTERDC_H */