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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Nobuhiro Iwamatsu72fd3832014-12-02 16:52:20 +09002/*
Nobuhiro Iwamatsua7da6f82016-04-01 03:51:33 +09003 * board/renesas/rcar-common/common.c
Nobuhiro Iwamatsu72fd3832014-12-02 16:52:20 +09004 *
5 * Copyright (C) 2013 Renesas Electronics Corporation
6 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Nobuhiro Iwamatsu581183d2016-04-01 03:51:34 +09007 * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsu72fd3832014-12-02 16:52:20 +09008 */
9
10#include <common.h>
11#include <asm/io.h>
12#include <asm/arch/sys_proto.h>
13#include <asm/arch/rmobile.h>
14#include <asm/arch/rcar-mstp.h>
15
16#define TSTR0 0x04
17#define TSTR0_STR0 0x01
18
Nobuhiro Iwamatsu8e2e5882014-12-02 16:52:24 +090019static struct mstp_ctl mstptbl[] = {
20 { SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA,
21 RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA },
22 { SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA,
23 RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA },
24 { SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA,
25 RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA },
26 { SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA,
27 RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA },
28 { SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA,
29 RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA },
30 { SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA,
31 RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA },
Nobuhiro Iwamatsu581183d2016-04-01 03:51:34 +090032#ifdef CONFIG_RCAR_GEN3
33 { SMSTPCR6, MSTP6_BITS, CONFIG_SMSTP6_ENA,
34 RMSTPCR6, MSTP6_BITS, CONFIG_RMSTP6_ENA },
35#endif
Nobuhiro Iwamatsu8e2e5882014-12-02 16:52:24 +090036 { SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA,
37 RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA },
38 { SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA,
39 RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA },
40 { SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA,
41 RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA },
42 { SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA,
43 RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA },
44 { SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA,
45 RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA },
46};
47
Nobuhiro Iwamatsu72fd3832014-12-02 16:52:20 +090048void arch_preboot_os(void)
49{
Nobuhiro Iwamatsu8e2e5882014-12-02 16:52:24 +090050 int i;
51
Nobuhiro Iwamatsu72fd3832014-12-02 16:52:20 +090052 /* stop TMU0 */
53 mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
54
Nobuhiro Iwamatsu8e2e5882014-12-02 16:52:24 +090055 /* Stop module clock */
56 for (i = 0; i < ARRAY_SIZE(mstptbl); i++) {
Nobuhiro Iwamatsu4ebaba52016-04-01 03:51:37 +090057 mstp_setclrbits_le32((uintptr_t)mstptbl[i].s_addr,
58 mstptbl[i].s_dis,
Nobuhiro Iwamatsu8e2e5882014-12-02 16:52:24 +090059 mstptbl[i].s_ena);
Nobuhiro Iwamatsu4ebaba52016-04-01 03:51:37 +090060 mstp_setclrbits_le32((uintptr_t)mstptbl[i].r_addr,
61 mstptbl[i].r_dis,
Nobuhiro Iwamatsu8e2e5882014-12-02 16:52:24 +090062 mstptbl[i].r_ena);
63 }
Nobuhiro Iwamatsu72fd3832014-12-02 16:52:20 +090064}