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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jagannadha Sutradharudu Tekif8f36c52014-01-09 01:48:26 +05302/*
3 * Xilinx Zynq 7000 DTSI
4 * Describes the hardware common to all Zynq 7000-based boards.
5 *
Michal Simek05e7ca62015-07-22 11:18:43 +02006 * Copyright (C) 2011 - 2015 Xilinx
Jagannadha Sutradharudu Tekif8f36c52014-01-09 01:48:26 +05307 */
Jagannadha Sutradharudu Tekif8f36c52014-01-09 01:48:26 +05308
9/ {
Michal Simekcc7978b2016-11-11 13:11:37 +010010 #address-cells = <1>;
11 #size-cells = <1>;
Jagannadha Sutradharudu Tekif8f36c52014-01-09 01:48:26 +053012 compatible = "xlnx,zynq-7000";
Masahiro Yamada580a54c2014-05-15 20:37:53 +090013
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
Moritz Fischer720ba462016-12-12 08:48:50 -080018 cpu0: cpu@0 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +090019 compatible = "arm,cortex-a9";
20 device_type = "cpu";
21 reg = <0>;
22 clocks = <&clkc 3>;
23 clock-latency = <1000>;
Michal Simekbece06c2015-07-22 10:38:45 +020024 cpu0-supply = <&regulator_vccpint>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +090025 operating-points = <
26 /* kHz uV */
27 666667 1000000
28 333334 1000000
Masahiro Yamada580a54c2014-05-15 20:37:53 +090029 >;
30 };
31
Moritz Fischer720ba462016-12-12 08:48:50 -080032 cpu1: cpu@1 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +090033 compatible = "arm,cortex-a9";
34 device_type = "cpu";
35 reg = <1>;
36 clocks = <&clkc 3>;
37 };
38 };
39
Michal Simek0b180d02017-02-14 17:40:21 +010040 fpga_full: fpga-full {
41 compatible = "fpga-region";
42 fpga-mgr = <&devcfg>;
43 #address-cells = <1>;
44 #size-cells = <1>;
45 ranges;
46 };
47
Michal Simekcc7978b2016-11-11 13:11:37 +010048 pmu@f8891000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +090049 compatible = "arm,cortex-a9-pmu";
50 interrupts = <0 5 4>, <0 6 4>;
51 interrupt-parent = <&intc>;
Michal Simek427d5682016-11-16 09:29:57 +010052 reg = <0xf8891000 0x1000>,
53 <0xf8893000 0x1000>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +090054 };
55
Michal Simekcc7978b2016-11-11 13:11:37 +010056 regulator_vccpint: fixedregulator {
Michal Simekbece06c2015-07-22 10:38:45 +020057 compatible = "regulator-fixed";
58 regulator-name = "VCCPINT";
59 regulator-min-microvolt = <1000000>;
60 regulator-max-microvolt = <1000000>;
61 regulator-boot-on;
62 regulator-always-on;
63 };
64
Michal Simek461c3882015-07-22 11:08:40 +020065 amba: amba {
Simon Glass035c6b22015-10-17 19:41:24 -060066 u-boot,dm-pre-reloc;
Masahiro Yamada580a54c2014-05-15 20:37:53 +090067 compatible = "simple-bus";
68 #address-cells = <1>;
69 #size-cells = <1>;
70 interrupt-parent = <&intc>;
71 ranges;
72
Michal Simekfb1a5062015-07-22 10:32:05 +020073 adc: adc@f8007100 {
74 compatible = "xlnx,zynq-xadc-1.00.a";
75 reg = <0xf8007100 0x20>;
76 interrupts = <0 7 4>;
77 interrupt-parent = <&intc>;
78 clocks = <&clkc 12>;
79 };
80
81 can0: can@e0008000 {
82 compatible = "xlnx,zynq-can-1.0";
83 status = "disabled";
84 clocks = <&clkc 19>, <&clkc 36>;
85 clock-names = "can_clk", "pclk";
86 reg = <0xe0008000 0x1000>;
87 interrupts = <0 28 4>;
88 interrupt-parent = <&intc>;
89 tx-fifo-depth = <0x40>;
90 rx-fifo-depth = <0x40>;
91 };
92
93 can1: can@e0009000 {
94 compatible = "xlnx,zynq-can-1.0";
95 status = "disabled";
96 clocks = <&clkc 20>, <&clkc 37>;
97 clock-names = "can_clk", "pclk";
98 reg = <0xe0009000 0x1000>;
99 interrupts = <0 51 4>;
100 interrupt-parent = <&intc>;
101 tx-fifo-depth = <0x40>;
102 rx-fifo-depth = <0x40>;
103 };
104
105 gpio0: gpio@e000a000 {
106 compatible = "xlnx,zynq-gpio-1.0";
107 #gpio-cells = <2>;
108 clocks = <&clkc 42>;
109 gpio-controller;
Michal Simek58fab4c2016-04-07 10:54:08 +0200110 interrupt-controller;
Michal Simek534f7e02017-11-02 09:24:12 +0100111 #interrupt-cells = <2>;
Michal Simekfb1a5062015-07-22 10:32:05 +0200112 interrupt-parent = <&intc>;
113 interrupts = <0 20 4>;
114 reg = <0xe000a000 0x1000>;
115 };
116
Michal Simeka0cb47f2015-07-22 10:28:48 +0200117 i2c0: i2c@e0004000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900118 compatible = "cdns,i2c-r1p10";
119 status = "disabled";
120 clocks = <&clkc 38>;
121 interrupt-parent = <&intc>;
122 interrupts = <0 25 4>;
123 reg = <0xe0004000 0x1000>;
124 #address-cells = <1>;
125 #size-cells = <0>;
126 };
127
Michal Simeka0cb47f2015-07-22 10:28:48 +0200128 i2c1: i2c@e0005000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900129 compatible = "cdns,i2c-r1p10";
130 status = "disabled";
131 clocks = <&clkc 39>;
132 interrupt-parent = <&intc>;
133 interrupts = <0 48 4>;
134 reg = <0xe0005000 0x1000>;
135 #address-cells = <1>;
136 #size-cells = <0>;
137 };
138
139 intc: interrupt-controller@f8f01000 {
140 compatible = "arm,cortex-a9-gic";
141 #interrupt-cells = <3>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900142 interrupt-controller;
143 reg = <0xF8F01000 0x1000>,
144 <0xF8F00100 0x100>;
145 };
146
Michal Simeka0cb47f2015-07-22 10:28:48 +0200147 L2: cache-controller@f8f02000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900148 compatible = "arm,pl310-cache";
149 reg = <0xF8F02000 0x1000>;
Michal Simekd50cb3d2015-07-22 11:26:08 +0200150 interrupts = <0 2 4>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900151 arm,data-latency = <3 2 2>;
152 arm,tag-latency = <2 2 2>;
153 cache-unified;
154 cache-level = <2>;
155 };
156
Michal Simekfb1a5062015-07-22 10:32:05 +0200157 mc: memory-controller@f8006000 {
158 compatible = "xlnx,zynq-ddrc-a05";
159 reg = <0xf8006000 0x1000>;
160 };
161
Michal Simeka0cb47f2015-07-22 10:28:48 +0200162 uart0: serial@e0000000 {
Michal Simek8a8c46a2015-07-22 10:40:51 +0200163 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900164 status = "disabled";
165 clocks = <&clkc 23>, <&clkc 40>;
Michal Simek8a8c46a2015-07-22 10:40:51 +0200166 clock-names = "uart_clk", "pclk";
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900167 reg = <0xE0000000 0x1000>;
168 interrupts = <0 27 4>;
169 };
170
Michal Simeka0cb47f2015-07-22 10:28:48 +0200171 uart1: serial@e0001000 {
Michal Simek8a8c46a2015-07-22 10:40:51 +0200172 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900173 status = "disabled";
174 clocks = <&clkc 24>, <&clkc 41>;
Michal Simek8a8c46a2015-07-22 10:40:51 +0200175 clock-names = "uart_clk", "pclk";
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900176 reg = <0xE0001000 0x1000>;
177 interrupts = <0 50 4>;
178 };
179
Jagan Tekia8a8fc92015-06-27 00:51:33 +0530180 spi0: spi@e0006000 {
Michal Simek40b383f2015-07-22 10:47:33 +0200181 compatible = "xlnx,zynq-spi-r1p6";
Jagan Tekia8a8fc92015-06-27 00:51:33 +0530182 reg = <0xe0006000 0x1000>;
183 status = "disabled";
184 interrupt-parent = <&intc>;
185 interrupts = <0 26 4>;
186 clocks = <&clkc 25>, <&clkc 34>;
187 clock-names = "ref_clk", "pclk";
188 #address-cells = <1>;
189 #size-cells = <0>;
190 };
191
192 spi1: spi@e0007000 {
Michal Simek40b383f2015-07-22 10:47:33 +0200193 compatible = "xlnx,zynq-spi-r1p6";
Jagan Tekia8a8fc92015-06-27 00:51:33 +0530194 reg = <0xe0007000 0x1000>;
195 status = "disabled";
196 interrupt-parent = <&intc>;
197 interrupts = <0 49 4>;
198 clocks = <&clkc 26>, <&clkc 35>;
199 clock-names = "ref_clk", "pclk";
200 #address-cells = <1>;
201 #size-cells = <0>;
202 };
203
Jagan Teki70676cb2015-08-15 23:02:31 +0530204 qspi: spi@e000d000 {
205 clock-names = "ref_clk", "pclk";
206 clocks = <&clkc 10>, <&clkc 43>;
207 compatible = "xlnx,zynq-qspi-1.0";
208 status = "disabled";
209 interrupt-parent = <&intc>;
210 interrupts = <0 19 4>;
211 reg = <0xe000d000 0x1000>;
212 #address-cells = <1>;
213 #size-cells = <0>;
214 };
215
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900216 gem0: ethernet@e000b000 {
Michal Simek7e163362015-07-22 10:51:16 +0200217 compatible = "cdns,zynq-gem", "cdns,gem";
Michal Simek08305fe2015-07-22 10:50:02 +0200218 reg = <0xe000b000 0x1000>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900219 status = "disabled";
220 interrupts = <0 22 4>;
221 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
222 clock-names = "pclk", "hclk", "tx_clk";
Michal Simek5ee236a2015-07-22 11:03:36 +0200223 #address-cells = <1>;
224 #size-cells = <0>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900225 };
226
227 gem1: ethernet@e000c000 {
Michal Simek7e163362015-07-22 10:51:16 +0200228 compatible = "cdns,zynq-gem", "cdns,gem";
Michal Simek08305fe2015-07-22 10:50:02 +0200229 reg = <0xe000c000 0x1000>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900230 status = "disabled";
231 interrupts = <0 45 4>;
232 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
233 clock-names = "pclk", "hclk", "tx_clk";
Michal Simek5ee236a2015-07-22 11:03:36 +0200234 #address-cells = <1>;
235 #size-cells = <0>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900236 };
237
Michal Simeka0cb47f2015-07-22 10:28:48 +0200238 sdhci0: sdhci@e0100000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900239 compatible = "arasan,sdhci-8.9a";
240 status = "disabled";
241 clock-names = "clk_xin", "clk_ahb";
242 clocks = <&clkc 21>, <&clkc 32>;
243 interrupt-parent = <&intc>;
244 interrupts = <0 24 4>;
245 reg = <0xe0100000 0x1000>;
Michal Simeke5c343d2016-01-14 13:06:28 +0100246 };
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900247
Michal Simeka0cb47f2015-07-22 10:28:48 +0200248 sdhci1: sdhci@e0101000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900249 compatible = "arasan,sdhci-8.9a";
250 status = "disabled";
251 clock-names = "clk_xin", "clk_ahb";
252 clocks = <&clkc 22>, <&clkc 33>;
253 interrupt-parent = <&intc>;
254 interrupts = <0 47 4>;
255 reg = <0xe0101000 0x1000>;
Michal Simeke5c343d2016-01-14 13:06:28 +0100256 };
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900257
258 slcr: slcr@f8000000 {
Stefan Herbrechtsmeier781745b2017-01-17 16:27:30 +0100259 u-boot,dm-pre-reloc;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900260 #address-cells = <1>;
261 #size-cells = <1>;
Masahiro Yamada621a93e2016-04-25 12:14:43 +0900262 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900263 reg = <0xF8000000 0x1000>;
264 ranges;
265 clkc: clkc@100 {
Stefan Herbrechtsmeier781745b2017-01-17 16:27:30 +0100266 u-boot,dm-pre-reloc;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900267 #clock-cells = <1>;
268 compatible = "xlnx,ps7-clkc";
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900269 fclk-enable = <0>;
270 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
271 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
272 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
273 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
274 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
275 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
276 "gem1_aper", "sdio0_aper", "sdio1_aper",
277 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
278 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
279 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
280 "dbg_trc", "dbg_apb";
281 reg = <0x100 0x100>;
282 };
Michal Simeke913ce22015-07-22 11:07:49 +0200283
Moritz Fischer4c987272015-07-30 18:13:55 -0700284 rstc: rstc@200 {
285 compatible = "xlnx,zynq-reset";
286 reg = <0x200 0x48>;
287 #reset-cells = <1>;
288 syscon = <&slcr>;
289 };
290
Michal Simeke913ce22015-07-22 11:07:49 +0200291 pinctrl0: pinctrl@700 {
292 compatible = "xlnx,pinctrl-zynq";
293 reg = <0x700 0x200>;
294 syscon = <&slcr>;
295 };
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900296 };
297
Michal Simekfb1a5062015-07-22 10:32:05 +0200298 dmac_s: dmac@f8003000 {
299 compatible = "arm,pl330", "arm,primecell";
300 reg = <0xf8003000 0x1000>;
301 interrupt-parent = <&intc>;
302 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
303 "dma4", "dma5", "dma6", "dma7";
304 interrupts = <0 13 4>,
305 <0 14 4>, <0 15 4>,
306 <0 16 4>, <0 17 4>,
307 <0 40 4>, <0 41 4>,
308 <0 42 4>, <0 43 4>;
309 #dma-cells = <1>;
310 #dma-channels = <8>;
311 #dma-requests = <4>;
312 clocks = <&clkc 27>;
313 clock-names = "apb_pclk";
314 };
315
316 devcfg: devcfg@f8007000 {
317 compatible = "xlnx,zynq-devcfg-1.0";
Michal Simek77bb73d2016-04-07 11:00:37 +0200318 interrupt-parent = <&intc>;
319 interrupts = <0 8 4>;
Michal Simekfb1a5062015-07-22 10:32:05 +0200320 reg = <0xf8007000 0x100>;
Michal Simek77bb73d2016-04-07 11:00:37 +0200321 clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
322 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
Moritz Fischer20fe3f12015-06-22 23:18:44 -0700323 syscon = <&slcr>;
Michal Simekfb1a5062015-07-22 10:32:05 +0200324 };
325
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900326 global_timer: timer@f8f00200 {
327 compatible = "arm,cortex-a9-global-timer";
328 reg = <0xf8f00200 0x20>;
329 interrupts = <1 11 0x301>;
330 interrupt-parent = <&intc>;
331 clocks = <&clkc 4>;
332 };
333
Michal Simeka0cb47f2015-07-22 10:28:48 +0200334 ttc0: timer@f8001000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900335 interrupt-parent = <&intc>;
Michal Simekb346bd12015-07-22 10:57:51 +0200336 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900337 compatible = "cdns,ttc";
338 clocks = <&clkc 6>;
339 reg = <0xF8001000 0x1000>;
340 };
341
Michal Simeka0cb47f2015-07-22 10:28:48 +0200342 ttc1: timer@f8002000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900343 interrupt-parent = <&intc>;
Michal Simekb346bd12015-07-22 10:57:51 +0200344 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900345 compatible = "cdns,ttc";
346 clocks = <&clkc 6>;
347 reg = <0xF8002000 0x1000>;
348 };
Michal Simekfb1a5062015-07-22 10:32:05 +0200349
Michal Simeka0cb47f2015-07-22 10:28:48 +0200350 scutimer: timer@f8f00600 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900351 interrupt-parent = <&intc>;
Michal Simeke5c343d2016-01-14 13:06:28 +0100352 interrupts = <1 13 0x301>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900353 compatible = "arm,cortex-a9-twd-timer";
Michal Simeke5c343d2016-01-14 13:06:28 +0100354 reg = <0xf8f00600 0x20>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900355 clocks = <&clkc 4>;
Michal Simeke5c343d2016-01-14 13:06:28 +0100356 };
Michal Simekfb1a5062015-07-22 10:32:05 +0200357
358 usb0: usb@e0002000 {
359 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
360 status = "disabled";
361 clocks = <&clkc 28>;
362 interrupt-parent = <&intc>;
363 interrupts = <0 21 4>;
364 reg = <0xe0002000 0x1000>;
365 phy_type = "ulpi";
366 };
367
368 usb1: usb@e0003000 {
369 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
370 status = "disabled";
371 clocks = <&clkc 29>;
372 interrupt-parent = <&intc>;
373 interrupts = <0 44 4>;
374 reg = <0xe0003000 0x1000>;
375 phy_type = "ulpi";
376 };
377
378 watchdog0: watchdog@f8005000 {
379 clocks = <&clkc 45>;
380 compatible = "cdns,wdt-r1p2";
381 interrupt-parent = <&intc>;
382 interrupts = <0 9 1>;
383 reg = <0xf8005000 0x1000>;
384 timeout-sec = <10>;
385 };
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900386 };
Jagannadha Sutradharudu Tekif8f36c52014-01-09 01:48:26 +0530387};