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gerrit.cesnet.cz / github / trini / u-boot / 83975d02e225e231960784972e7820a8b303756b / . / board / m501sk / memsetup.S
blob: 6aea723f91f07944c3f9c037fa8ede9a2d8c88c3 [file] [log] [blame]
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000[diff] [blame]1/*
2 * Memory Setup stuff - taken from blob memsetup.S
3 *
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
6 *
7 * Modified for the at91rm9200dk board by
8 * (C) Copyright 2004
9 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#include <config.h>
31#include <version.h>
32
33#ifdef CONFIG_BOOTBINFUNC
34/*
35 * some parameters for the board
36 *
37 * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
38 * turn is based on the boot.bin code from ATMEL
39 *
40 */
41
42/* flash */
43#define MC_PUIA 0xFFFFFF10
44#define MC_PUIA_VAL 0x00000000
45#define MC_PUP 0xFFFFFF50
46#define MC_PUP_VAL 0x00000000
47#define MC_PUER 0xFFFFFF54
48#define MC_PUER_VAL 0x00000000
49#define MC_ASR 0xFFFFFF04
50#define MC_ASR_VAL 0x00000000
51#define MC_AASR 0xFFFFFF08
52#define MC_AASR_VAL 0x00000000
53#define EBI_CFGR 0xFFFFFF64
54#define EBI_CFGR_VAL 0x00000000
Jean-Christophe PLAGNIOL-VILLARDf1b985f2008-03-30 16:39:53 +0200[diff] [blame]55#define SMC_CSR0 0xFFFFFF70
56#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000[diff] [blame]57
58/* clocks */
59#define PLLAR 0xFFFFFC28
60#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
61#define PLLBR 0xFFFFFC2C
62#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
63#define MCKR 0xFFFFFC30
64/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
65#define MCKR_VAL 0x00000202
66
67/* sdram */
68#define PIOC_ASR 0xFFFFF870
69#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */
70#define PIOC_BSR 0xFFFFF874
71#define PIOC_BSR_VAL 0x00000000
72#define PIOC_PDR 0xFFFFF804
73#define PIOC_PDR_VAL 0xFFFF0000
74#define EBI_CSA 0xFFFFFF60
75#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
76#define SDRC_CR 0xFFFFFF98
77#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
78#define SDRAM 0x20000000 /* address of the SDRAM */
79#define SDRAM1 0x20000080 /* address of the SDRAM */
80#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
81#define SDRC_MR 0xFFFFFF90
82#define SDRC_MR_VAL 0x00000002 /* Precharge All */
83#define SDRC_MR_VAL1 0x00000004 /* refresh */
84#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
85#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
86#define SDRC_TR 0xFFFFFF94
87#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
88
89_TEXT_BASE:
90 .word TEXT_BASE
91
92.globl lowlevelinit
93lowlevelinit:
94 /* memory control configuration */
95 /* this isn't very elegant, but what the heck */
96 ldr r0, =SMRDATA
97 ldr r1, _TEXT_BASE
98 sub r0, r0, r1
99 add r2, r0, #80
1000:
101 /* the address */
102 ldr r1, [r0], #4
103 /* the value */
104 ldr r3, [r0], #4
105 str r3, [r1]
106 cmp r2, r0
107 bne 0b
108 /* delay - this is all done by guess */
109 ldr r0, =0x00010000
1101:
111 subs r0, r0, #1
112 bhi 1b
113 ldr r0, =SMRDATA1
114 ldr r1, _TEXT_BASE
115 sub r0, r0, r1
116 add r2, r0, #176
1172:
118 /* the address */
119 ldr r1, [r0], #4
120 /* the value */
121 ldr r3, [r0], #4
122 str r3, [r1]
123 cmp r2, r0
124 bne 2b
125
126 /* everything is fine now */
127 mov pc, lr
128
129 .ltorg
130
131SMRDATA:
132 .word MC_PUIA
133 .word MC_PUIA_VAL
134 .word MC_PUP
135 .word MC_PUP_VAL
136 .word MC_PUER
137 .word MC_PUER_VAL
138 .word MC_ASR
139 .word MC_ASR_VAL
140 .word MC_AASR
141 .word MC_AASR_VAL
142 .word EBI_CFGR
143 .word EBI_CFGR_VAL
Jean-Christophe PLAGNIOL-VILLARDf1b985f2008-03-30 16:39:53 +0200[diff] [blame]144 .word SMC_CSR0
145 .word SMC_CSR0_VAL
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000[diff] [blame]146 .word PLLAR
147 .word PLLAR_VAL
148 .word PLLBR
149 .word PLLBR_VAL
150 .word MCKR
151 .word MCKR_VAL
152 /* SMRDATA is 80 bytes long */
153 /* here there's a delay of 100 */
154SMRDATA1:
155 .word PIOC_ASR
156 .word PIOC_ASR_VAL
157 .word PIOC_BSR
158 .word PIOC_BSR_VAL
159 .word PIOC_PDR
160 .word PIOC_PDR_VAL
161 .word EBI_CSA
162 .word EBI_CSA_VAL
163 .word SDRC_CR
164 .word SDRC_CR_VAL
165 .word SDRC_MR
166 .word SDRC_MR_VAL
167 .word SDRAM
168 .word SDRAM_VAL
169 .word SDRC_MR
170 .word SDRC_MR_VAL1
171 .word SDRAM
172 .word SDRAM_VAL
173 .word SDRAM
174 .word SDRAM_VAL
175 .word SDRAM
176 .word SDRAM_VAL
177 .word SDRAM
178 .word SDRAM_VAL
179 .word SDRAM
180 .word SDRAM_VAL
181 .word SDRAM
182 .word SDRAM_VAL
183 .word SDRAM
184 .word SDRAM_VAL
185 .word SDRAM
186 .word SDRAM_VAL
187 .word SDRC_MR
188 .word SDRC_MR_VAL2
189 .word SDRAM1
190 .word SDRAM_VAL
191 .word SDRC_TR
192 .word SDRC_TR_VAL
193 .word SDRAM
194 .word SDRAM_VAL
195 .word SDRC_MR
196 .word SDRC_MR_VAL3
197 .word SDRAM
198 .word SDRAM_VAL
199 /* SMRDATA1 is 176 bytes long */
200#endif /* CONFIG_BOOTBINFUNC */