wdenk | b2184c3 | 2002-11-19 23:01:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
Albert ARIBAUD | fa82f87 | 2011-08-04 18:45:45 +0200 | [diff] [blame] | 3 | * Daniel Engström, Omicron Ceti AB, daniel@omicron.se |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | b2184c3 | 2002-11-19 23:01:07 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __ASM_PROCESSOR_H_ |
| 9 | #define __ASM_PROCESSOR_H_ 1 |
Graeme Russ | c53fd2b | 2011-02-12 15:11:30 +1100 | [diff] [blame] | 10 | |
Simon Glass | e34aef1 | 2014-11-14 20:56:29 -0700 | [diff] [blame] | 11 | #define X86_GDT_ENTRY_SIZE 8 |
Graeme Russ | 109ad14 | 2011-12-31 10:24:36 +1100 | [diff] [blame] | 12 | |
Simon Glass | e34aef1 | 2014-11-14 20:56:29 -0700 | [diff] [blame] | 13 | #define X86_GDT_ENTRY_NULL 0 |
| 14 | #define X86_GDT_ENTRY_UNUSED 1 |
| 15 | #define X86_GDT_ENTRY_32BIT_CS 2 |
| 16 | #define X86_GDT_ENTRY_32BIT_DS 3 |
| 17 | #define X86_GDT_ENTRY_32BIT_FS 4 |
| 18 | #define X86_GDT_ENTRY_16BIT_CS 5 |
| 19 | #define X86_GDT_ENTRY_16BIT_DS 6 |
| 20 | #define X86_GDT_ENTRY_16BIT_FLAT_CS 7 |
| 21 | #define X86_GDT_ENTRY_16BIT_FLAT_DS 8 |
| 22 | #define X86_GDT_NUM_ENTRIES 9 |
Graeme Russ | 109ad14 | 2011-12-31 10:24:36 +1100 | [diff] [blame] | 23 | |
| 24 | #define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE) |
Graeme Russ | c53fd2b | 2011-02-12 15:11:30 +1100 | [diff] [blame] | 25 | |
Simon Glass | 45b5a37 | 2015-04-29 22:25:59 -0600 | [diff] [blame] | 26 | /* Length of the public header on Intel microcode blobs */ |
| 27 | #define UCODE_HEADER_LEN 0x30 |
| 28 | |
Simon Glass | 21b9b14 | 2014-11-10 18:00:24 -0700 | [diff] [blame] | 29 | #ifndef __ASSEMBLY__ |
| 30 | |
Simon Glass | ff6a8f3 | 2015-04-28 20:11:29 -0600 | [diff] [blame] | 31 | /* |
| 32 | * This register is documented in (for example) the Intel Atom Processor E3800 |
| 33 | * Product Family Datasheet in "PCU - Power Management Controller (PMC)". |
| 34 | * |
| 35 | * RST_CNT: Reset Control Register (RST_CNT) Offset cf9. |
| 36 | * |
| 37 | * The naming follows Intel's naming. |
| 38 | */ |
Simon Glass | f5fbbe9 | 2014-11-12 22:42:19 -0700 | [diff] [blame] | 39 | #define PORT_RESET 0xcf9 |
| 40 | |
Simon Glass | ff6a8f3 | 2015-04-28 20:11:29 -0600 | [diff] [blame] | 41 | enum { |
| 42 | SYS_RST = 1 << 1, /* 0 for soft reset, 1 for hard reset */ |
| 43 | RST_CPU = 1 << 2, /* initiate reset */ |
| 44 | FULL_RST = 1 << 3, /* full power cycle */ |
| 45 | }; |
| 46 | |
| 47 | /** |
| 48 | * x86_full_reset() - reset everything: perform a full power cycle |
| 49 | */ |
| 50 | void x86_full_reset(void); |
| 51 | |
Simon Glass | 21b9b14 | 2014-11-10 18:00:24 -0700 | [diff] [blame] | 52 | static inline __attribute__((always_inline)) void cpu_hlt(void) |
| 53 | { |
| 54 | asm("hlt"); |
| 55 | } |
| 56 | |
| 57 | static inline ulong cpu_get_sp(void) |
| 58 | { |
| 59 | ulong result; |
| 60 | |
| 61 | asm volatile( |
| 62 | "mov %%esp, %%eax" |
| 63 | : "=a" (result)); |
| 64 | return result; |
| 65 | } |
| 66 | |
| 67 | #endif /* __ASSEMBLY__ */ |
| 68 | |
wdenk | b2184c3 | 2002-11-19 23:01:07 +0000 | [diff] [blame] | 69 | #endif |