blob: db1f85125f9a57d67e66b232db4b48e50b7e2014 [file] [log] [blame]
Sukumar Ghoraide941242010-09-18 20:32:33 -07001/*
2 * (C) Copyright 2008
3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
12 * the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <common.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070027#include <cpu_func.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060028#include <log.h>
Pantelis Antoniou93bfd612014-03-11 19:34:20 +020029#include <malloc.h>
Kishon Vijay Abraham If0d53e82017-09-21 16:51:34 +020030#include <memalign.h>
Sukumar Ghoraide941242010-09-18 20:32:33 -070031#include <mmc.h>
32#include <part.h>
33#include <i2c.h>
Felix Brack339d5782017-10-11 17:05:28 +020034#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
Nishanth Menoncb199102013-03-26 05:20:54 +000035#include <palmas.h>
Felix Brack339d5782017-10-11 17:05:28 +020036#endif
Simon Glass90526e92020-05-10 11:39:56 -060037#include <asm/cache.h>
Sukumar Ghoraide941242010-09-18 20:32:33 -070038#include <asm/io.h>
39#include <asm/arch/mmc_host_def.h>
Kishon Vijay Abraham I33c1d772018-01-30 16:01:40 +010040#ifdef CONFIG_OMAP54XX
41#include <asm/arch/mux_dra7xx.h>
42#include <asm/arch/dra7xx_iodelay.h>
43#endif
Roger Quadros3b689392015-09-19 16:26:53 +053044#if !defined(CONFIG_SOC_KEYSTONE)
45#include <asm/gpio.h>
Dirk Behme96e0e7b2011-05-15 09:04:47 +000046#include <asm/arch/sys_proto.h>
Roger Quadros3b689392015-09-19 16:26:53 +053047#endif
Tom Rini2a48b3a2017-02-09 13:41:28 -050048#ifdef CONFIG_MMC_OMAP36XX_PINS
49#include <asm/arch/mux.h>
50#endif
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +053051#include <dm.h>
Simon Glass61b29b82020-02-03 07:36:15 -070052#include <dm/devres.h>
Simon Glasscd93d622020-05-10 11:40:13 -060053#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060054#include <linux/delay.h>
Simon Glass61b29b82020-02-03 07:36:15 -070055#include <linux/err.h>
Jean-Jacques Hiblot42182c92018-01-30 16:01:44 +010056#include <power/regulator.h>
Faiz Abbas351a4aa2019-01-30 18:08:42 +053057#include <thermal.h>
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +053058
59DECLARE_GLOBAL_DATA_PTR;
Sukumar Ghoraide941242010-09-18 20:32:33 -070060
Pantelis Antoniouab769f22014-02-26 19:28:45 +020061/* simplify defines to OMAP_HSMMC_USE_GPIO */
62#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
63 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
64#define OMAP_HSMMC_USE_GPIO
65#else
66#undef OMAP_HSMMC_USE_GPIO
67#endif
68
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +000069/* common definitions for all OMAPs */
70#define SYSCTL_SRC (1 << 25)
71#define SYSCTL_SRD (1 << 26)
72
Kishon Vijay Abraham I33c1d772018-01-30 16:01:40 +010073#ifdef CONFIG_IODELAY_RECALIBRATION
74struct omap_hsmmc_pinctrl_state {
75 struct pad_conf_entry *padconf;
76 int npads;
77 struct iodelay_cfg_entry *iodelay;
78 int niodelays;
79};
80#endif
81
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +000082struct omap_hsmmc_data {
83 struct hsmmc *base_addr;
Simon Glassc4d660d2017-07-04 13:31:19 -060084#if !CONFIG_IS_ENABLED(DM_MMC)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +020085 struct mmc_config cfg;
Jean-Jacques Hiblot3d673ff2017-03-22 16:00:33 +010086#endif
Kishon Vijay Abraham I48a2f112018-01-30 16:01:31 +010087 uint bus_width;
Jean-Jacques Hiblot5baf5432018-01-30 16:01:30 +010088 uint clock;
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +010089 ushort last_cmd;
Pantelis Antoniouab769f22014-02-26 19:28:45 +020090#ifdef OMAP_HSMMC_USE_GPIO
Simon Glassc4d660d2017-07-04 13:31:19 -060091#if CONFIG_IS_ENABLED(DM_MMC)
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +053092 struct gpio_desc cd_gpio; /* Change Detect GPIO */
93 struct gpio_desc wp_gpio; /* Write Protect GPIO */
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +053094#else
Nikita Kiryanove874d5b2012-12-03 02:19:44 +000095 int cd_gpio;
Nikita Kiryanove3913f52012-12-03 02:19:47 +000096 int wp_gpio;
Pantelis Antoniouab769f22014-02-26 19:28:45 +020097#endif
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +053098#endif
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +010099#if CONFIG_IS_ENABLED(DM_MMC)
Jean-Jacques Hiblot8fc238b2018-01-30 16:01:33 +0100100 enum bus_mode mode;
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +0100101#endif
Kishon Vijay Abraham If0d53e82017-09-21 16:51:34 +0200102 u8 controller_flags;
Jean-Jacques Hiblot27a4b3b2018-02-23 10:40:18 +0100103#ifdef CONFIG_MMC_OMAP_HS_ADMA
Kishon Vijay Abraham If0d53e82017-09-21 16:51:34 +0200104 struct omap_hsmmc_adma_desc *adma_desc_table;
105 uint desc_slot;
106#endif
Kishon Vijay Abraham I2d28eed2018-01-30 16:01:41 +0100107 const char *hw_rev;
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +0100108 struct udevice *pbias_supply;
109 uint signal_voltage;
Kishon Vijay Abraham I33c1d772018-01-30 16:01:40 +0100110#ifdef CONFIG_IODELAY_RECALIBRATION
111 struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
112 struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
113 struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
114 struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
115 struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
116 struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
117 struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
118 struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
119 struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
120#endif
121};
122
123struct omap_mmc_of_data {
124 u8 controller_flags;
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000125};
126
Jean-Jacques Hiblot27a4b3b2018-02-23 10:40:18 +0100127#ifdef CONFIG_MMC_OMAP_HS_ADMA
Kishon Vijay Abraham If0d53e82017-09-21 16:51:34 +0200128struct omap_hsmmc_adma_desc {
129 u8 attr;
130 u8 reserved;
131 u16 len;
132 u32 addr;
133};
134
135#define ADMA_MAX_LEN 63488
136
137/* Decriptor table defines */
138#define ADMA_DESC_ATTR_VALID BIT(0)
139#define ADMA_DESC_ATTR_END BIT(1)
140#define ADMA_DESC_ATTR_INT BIT(2)
141#define ADMA_DESC_ATTR_ACT1 BIT(4)
142#define ADMA_DESC_ATTR_ACT2 BIT(5)
143
144#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
145#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
146#endif
147
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500148/* If we fail after 1 second wait, something is really bad */
149#define MAX_RETRY_MS 1000
Jean-Jacques Hiblota4efd732018-01-30 16:01:37 +0100150#define MMC_TIMEOUT_MS 20
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500151
Kishon Vijay Abraham If0d53e82017-09-21 16:51:34 +0200152/* DMA transfers can take a long time if a lot a data is transferred.
153 * The timeout must take in account the amount of data. Let's assume
154 * that the time will never exceed 333 ms per MB (in other word we assume
155 * that the bandwidth is always above 3MB/s).
156 */
157#define DMA_TIMEOUT_PER_MB 333
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +0100158#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
159#define OMAP_HSMMC_NO_1_8_V BIT(1)
Kishon Vijay Abraham If0d53e82017-09-21 16:51:34 +0200160#define OMAP_HSMMC_USE_ADMA BIT(2)
Kishon Vijay Abraham I33c1d772018-01-30 16:01:40 +0100161#define OMAP_HSMMC_REQUIRE_IODELAY BIT(3)
Kishon Vijay Abraham If0d53e82017-09-21 16:51:34 +0200162
Sricharan933efe62011-11-15 09:49:53 -0500163static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
164static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
165 unsigned int siz);
Jean-Jacques Hiblot5baf5432018-01-30 16:01:30 +0100166static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
167static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
Jean-Jacques Hiblot14761ca2018-01-30 16:01:35 +0100168static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
Balaji T K14fa2dd2011-09-08 06:34:57 +0000169
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +0100170static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
171{
Simon Glassc4d660d2017-07-04 13:31:19 -0600172#if CONFIG_IS_ENABLED(DM_MMC)
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +0100173 return dev_get_priv(mmc->dev);
174#else
175 return (struct omap_hsmmc_data *)mmc->priv;
176#endif
177}
Tom Rini2af17e22020-06-04 16:03:55 -0400178
179#if defined(CONFIG_OMAP34XX) || defined(CONFIG_IODELAY_RECALIBRATION)
Jean-Jacques Hiblot3d673ff2017-03-22 16:00:33 +0100180static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
181{
Simon Glassc4d660d2017-07-04 13:31:19 -0600182#if CONFIG_IS_ENABLED(DM_MMC)
Jean-Jacques Hiblot3d673ff2017-03-22 16:00:33 +0100183 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
184 return &plat->cfg;
185#else
186 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
187#endif
188}
Tom Rini2af17e22020-06-04 16:03:55 -0400189#endif
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +0100190
Simon Glassc4d660d2017-07-04 13:31:19 -0600191#if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
Nikita Kiryanove874d5b2012-12-03 02:19:44 +0000192static int omap_mmc_setup_gpio_in(int gpio, const char *label)
193{
Simon Glass5915a2a2014-10-22 21:37:09 -0600194 int ret;
195
Simon Glassbcee8d62019-12-06 21:41:35 -0700196#if !CONFIG_IS_ENABLED(DM_GPIO)
Nikita Kiryanove874d5b2012-12-03 02:19:44 +0000197 if (!gpio_is_valid(gpio))
198 return -1;
Simon Glass5915a2a2014-10-22 21:37:09 -0600199#endif
200 ret = gpio_request(gpio, label);
201 if (ret)
202 return ret;
Nikita Kiryanove874d5b2012-12-03 02:19:44 +0000203
Simon Glass5915a2a2014-10-22 21:37:09 -0600204 ret = gpio_direction_input(gpio);
205 if (ret)
206 return ret;
Nikita Kiryanove874d5b2012-12-03 02:19:44 +0000207
208 return gpio;
209}
Nikita Kiryanove874d5b2012-12-03 02:19:44 +0000210#endif
211
Jeroen Hofstee750121c2014-07-12 21:24:08 +0200212static unsigned char mmc_board_init(struct mmc *mmc)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700213{
Sukumar Ghoraide941242010-09-18 20:32:33 -0700214#if defined(CONFIG_OMAP34XX)
Jean-Jacques Hiblot3d673ff2017-03-22 16:00:33 +0100215 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
Sukumar Ghoraide941242010-09-18 20:32:33 -0700216 t2_t *t2_base = (t2_t *)T2_BASE;
217 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
Grazvydas Ignotasb1e725f2012-03-19 03:50:53 +0000218 u32 pbias_lite;
Adam Ford6aca17c2017-02-06 11:31:43 -0600219#ifdef CONFIG_MMC_OMAP36XX_PINS
220 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
221#endif
Sukumar Ghoraide941242010-09-18 20:32:33 -0700222
Grazvydas Ignotasb1e725f2012-03-19 03:50:53 +0000223 pbias_lite = readl(&t2_base->pbias_lite);
224 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
Albert ARIBAUD \(3ADEV\)5bfdd1f2015-01-16 09:09:50 +0100225#ifdef CONFIG_TARGET_OMAP3_CAIRO
226 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
227 pbias_lite &= ~PBIASLITEVMODE0;
228#endif
Adam Ford03190a72018-09-05 04:11:08 -0500229#ifdef CONFIG_TARGET_OMAP3_LOGIC
230 /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
231 pbias_lite &= ~PBIASLITEVMODE1;
232#endif
Adam Ford6aca17c2017-02-06 11:31:43 -0600233#ifdef CONFIG_MMC_OMAP36XX_PINS
234 if (get_cpu_family() == CPU_OMAP36XX) {
235 /* Disable extended drain IO before changing PBIAS */
236 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
237 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
238 }
239#endif
Grazvydas Ignotasb1e725f2012-03-19 03:50:53 +0000240 writel(pbias_lite, &t2_base->pbias_lite);
Paul Kocialkowskiaac54502014-11-08 20:55:47 +0100241
Grazvydas Ignotasb1e725f2012-03-19 03:50:53 +0000242 writel(pbias_lite | PBIASLITEPWRDNZ1 |
Sukumar Ghoraide941242010-09-18 20:32:33 -0700243 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
244 &t2_base->pbias_lite);
245
Adam Ford6aca17c2017-02-06 11:31:43 -0600246#ifdef CONFIG_MMC_OMAP36XX_PINS
247 if (get_cpu_family() == CPU_OMAP36XX)
248 /* Enable extended drain IO after changing PBIAS */
249 writel(wkup_ctrl |
250 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
251 OMAP34XX_CTRL_WKUP_CTRL);
252#endif
Sukumar Ghoraide941242010-09-18 20:32:33 -0700253 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
254 &t2_base->devconf0);
255
256 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
257 &t2_base->devconf1);
258
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +0000259 /* Change from default of 52MHz to 26MHz if necessary */
Jean-Jacques Hiblot3d673ff2017-03-22 16:00:33 +0100260 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +0000261 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
262 &t2_base->ctl_prog_io1);
263
Sukumar Ghoraide941242010-09-18 20:32:33 -0700264 writel(readl(&prcm_base->fclken1_core) |
265 EN_MMC1 | EN_MMC2 | EN_MMC3,
266 &prcm_base->fclken1_core);
267
268 writel(readl(&prcm_base->iclken1_core) |
269 EN_MMC1 | EN_MMC2 | EN_MMC3,
270 &prcm_base->iclken1_core);
271#endif
272
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +0100273#if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
274 !CONFIG_IS_ENABLED(DM_REGULATOR)
Balaji T K14fa2dd2011-09-08 06:34:57 +0000275 /* PBIAS config needed for MMC1 only */
Jean-Jacques Hiblotdc091272017-03-22 16:00:32 +0100276 if (mmc_get_blk_desc(mmc)->devnum == 0)
Faiz Abbasd2c05f52019-04-05 14:18:46 +0530277 vmmc_pbias_config(LDO_VOLT_3V3);
Balaji T Kdd23e592012-03-12 02:25:49 +0000278#endif
Sukumar Ghoraide941242010-09-18 20:32:33 -0700279
280 return 0;
281}
282
Sricharan933efe62011-11-15 09:49:53 -0500283void mmc_init_stream(struct hsmmc *mmc_base)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700284{
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500285 ulong start;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700286
287 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
288
289 writel(MMC_CMD0, &mmc_base->cmd);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500290 start = get_timer(0);
291 while (!(readl(&mmc_base->stat) & CC_MASK)) {
292 if (get_timer(0) - start > MAX_RETRY_MS) {
293 printf("%s: timedout waiting for cc!\n", __func__);
294 return;
295 }
296 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700297 writel(CC_MASK, &mmc_base->stat)
298 ;
299 writel(MMC_CMD0, &mmc_base->cmd)
300 ;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500301 start = get_timer(0);
302 while (!(readl(&mmc_base->stat) & CC_MASK)) {
303 if (get_timer(0) - start > MAX_RETRY_MS) {
304 printf("%s: timedout waiting for cc2!\n", __func__);
305 return;
306 }
307 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700308 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
309}
310
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +0100311#if CONFIG_IS_ENABLED(DM_MMC)
Kishon Vijay Abraham I33c1d772018-01-30 16:01:40 +0100312#ifdef CONFIG_IODELAY_RECALIBRATION
313static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
314{
315 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
316 struct omap_hsmmc_pinctrl_state *pinctrl_state;
317
318 switch (priv->mode) {
319 case MMC_HS_200:
320 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
321 break;
322 case UHS_SDR104:
323 pinctrl_state = priv->sdr104_pinctrl_state;
324 break;
325 case UHS_SDR50:
326 pinctrl_state = priv->sdr50_pinctrl_state;
327 break;
328 case UHS_DDR50:
329 pinctrl_state = priv->ddr50_pinctrl_state;
330 break;
331 case UHS_SDR25:
332 pinctrl_state = priv->sdr25_pinctrl_state;
333 break;
334 case UHS_SDR12:
335 pinctrl_state = priv->sdr12_pinctrl_state;
336 break;
337 case SD_HS:
338 case MMC_HS:
339 case MMC_HS_52:
340 pinctrl_state = priv->hs_pinctrl_state;
341 break;
342 case MMC_DDR_52:
343 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
344 default:
345 pinctrl_state = priv->default_pinctrl_state;
346 break;
347 }
348
Jean-Jacques Hiblotbcc6bd82018-01-30 16:01:42 +0100349 if (!pinctrl_state)
350 pinctrl_state = priv->default_pinctrl_state;
351
Kishon Vijay Abraham I33c1d772018-01-30 16:01:40 +0100352 if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
353 if (pinctrl_state->iodelay)
354 late_recalibrate_iodelay(pinctrl_state->padconf,
355 pinctrl_state->npads,
356 pinctrl_state->iodelay,
357 pinctrl_state->niodelays);
358 else
359 do_set_mux32((*ctrl)->control_padconf_core_base,
360 pinctrl_state->padconf,
361 pinctrl_state->npads);
362 }
363}
364#endif
Jean-Jacques Hiblot8fc238b2018-01-30 16:01:33 +0100365static void omap_hsmmc_set_timing(struct mmc *mmc)
366{
367 u32 val;
368 struct hsmmc *mmc_base;
369 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
370
371 mmc_base = priv->base_addr;
372
Kishon Vijay Abraham I33c1d772018-01-30 16:01:40 +0100373 omap_hsmmc_stop_clock(mmc_base);
Jean-Jacques Hiblot8fc238b2018-01-30 16:01:33 +0100374 val = readl(&mmc_base->ac12);
375 val &= ~AC12_UHSMC_MASK;
376 priv->mode = mmc->selected_mode;
377
Kishon Vijay Abraham I9b3fc212018-01-30 16:01:34 +0100378 if (mmc_is_mode_ddr(priv->mode))
379 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
380 else
381 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
382
Jean-Jacques Hiblot8fc238b2018-01-30 16:01:33 +0100383 switch (priv->mode) {
384 case MMC_HS_200:
385 case UHS_SDR104:
386 val |= AC12_UHSMC_SDR104;
387 break;
388 case UHS_SDR50:
389 val |= AC12_UHSMC_SDR50;
390 break;
391 case MMC_DDR_52:
392 case UHS_DDR50:
393 val |= AC12_UHSMC_DDR50;
394 break;
395 case SD_HS:
396 case MMC_HS_52:
397 case UHS_SDR25:
398 val |= AC12_UHSMC_SDR25;
399 break;
400 case MMC_LEGACY:
401 case MMC_HS:
Jean-Jacques Hiblot8fc238b2018-01-30 16:01:33 +0100402 case UHS_SDR12:
403 val |= AC12_UHSMC_SDR12;
404 break;
405 default:
406 val |= AC12_UHSMC_RES;
407 break;
408 }
409 writel(val, &mmc_base->ac12);
Kishon Vijay Abraham I33c1d772018-01-30 16:01:40 +0100410
411#ifdef CONFIG_IODELAY_RECALIBRATION
412 omap_hsmmc_io_recalibrate(mmc);
413#endif
414 omap_hsmmc_start_clock(mmc_base);
Jean-Jacques Hiblot8fc238b2018-01-30 16:01:33 +0100415}
416
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +0100417static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +0100418{
419 struct hsmmc *mmc_base;
420 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +0100421 u32 hctl, ac12;
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +0100422
423 mmc_base = priv->base_addr;
424
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +0100425 hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
426 ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +0100427
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +0100428 switch (signal_voltage) {
429 case MMC_SIGNAL_VOLTAGE_330:
Faiz Abbasd2c05f52019-04-05 14:18:46 +0530430 hctl |= SDVS_3V3;
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +0100431 break;
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +0100432 case MMC_SIGNAL_VOLTAGE_180:
433 hctl |= SDVS_1V8;
434 ac12 |= AC12_V1V8_SIGEN;
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +0100435 break;
436 }
437
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +0100438 writel(hctl, &mmc_base->hctl);
439 writel(ac12, &mmc_base->ac12);
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +0100440}
441
Sam Protsenko6cf8a902019-08-14 22:52:51 +0300442static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +0100443{
444 int ret = -ETIMEDOUT;
445 u32 con;
446 bool dat0_high;
447 bool target_dat0_high = !!state;
448 struct omap_hsmmc_data *priv = dev_get_priv(dev);
449 struct hsmmc *mmc_base = priv->base_addr;
450
451 con = readl(&mmc_base->con);
452 writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
453
Sam Protsenko6cf8a902019-08-14 22:52:51 +0300454 timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
455 while (timeout_us--) {
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +0100456 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
457 if (dat0_high == target_dat0_high) {
458 ret = 0;
459 break;
460 }
461 udelay(10);
462 }
463 writel(con, &mmc_base->con);
464
465 return ret;
466}
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +0100467
468#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
469#if CONFIG_IS_ENABLED(DM_REGULATOR)
470static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
471{
472 int ret = 0;
473 int uV = mV * 1000;
474
475 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
476
477 if (!mmc->vqmmc_supply)
478 return 0;
479
480 /* Disable PBIAS */
Lokesh Vutlad3de3852019-01-11 15:15:52 +0530481 ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
482 if (ret)
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +0100483 return ret;
484
485 /* Turn off IO voltage */
Lokesh Vutlad3de3852019-01-11 15:15:52 +0530486 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
487 if (ret)
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +0100488 return ret;
489 /* Program a new IO voltage value */
490 ret = regulator_set_value(mmc->vqmmc_supply, uV);
491 if (ret)
492 return ret;
493 /* Turn on IO voltage */
Lokesh Vutlad3de3852019-01-11 15:15:52 +0530494 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
495 if (ret)
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +0100496 return ret;
497
498 /* Program PBIAS voltage*/
499 ret = regulator_set_value(priv->pbias_supply, uV);
500 if (ret && ret != -ENOSYS)
501 return ret;
502 /* Enable PBIAS */
Lokesh Vutlad3de3852019-01-11 15:15:52 +0530503 ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
504 if (ret)
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +0100505 return ret;
506
507 return 0;
508}
509#endif
510
511static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
512{
513 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
514 struct hsmmc *mmc_base = priv->base_addr;
515 int mv = mmc_voltage_to_mv(mmc->signal_voltage);
516 u32 capa_mask;
517 __maybe_unused u8 palmas_ldo_volt;
518 u32 val;
519
520 if (mv < 0)
521 return -EINVAL;
522
523 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
Faiz Abbasd2c05f52019-04-05 14:18:46 +0530524 mv = 3300;
525 capa_mask = VS33_3V3SUP;
526 palmas_ldo_volt = LDO_VOLT_3V3;
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +0100527 } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
528 capa_mask = VS18_1V8SUP;
529 palmas_ldo_volt = LDO_VOLT_1V8;
530 } else {
531 return -EOPNOTSUPP;
532 }
533
534 val = readl(&mmc_base->capa);
535 if (!(val & capa_mask))
536 return -EOPNOTSUPP;
537
538 priv->signal_voltage = mmc->signal_voltage;
539
540 omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
541
542#if CONFIG_IS_ENABLED(DM_REGULATOR)
543 return omap_hsmmc_set_io_regulator(mmc, mv);
544#elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
545 defined(CONFIG_PALMAS_POWER)
546 if (mmc_get_blk_desc(mmc)->devnum == 0)
547 vmmc_pbias_config(palmas_ldo_volt);
548 return 0;
549#else
550 return 0;
551#endif
552}
553#endif
554
555static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +0100556{
557 struct hsmmc *mmc_base;
558 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
559 u32 val;
560
561 mmc_base = priv->base_addr;
562 val = readl(&mmc_base->capa);
563
564 if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
Faiz Abbasd2c05f52019-04-05 14:18:46 +0530565 val |= (VS33_3V3SUP | VS18_1V8SUP);
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +0100566 } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
Faiz Abbasd2c05f52019-04-05 14:18:46 +0530567 val |= VS33_3V3SUP;
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +0100568 val &= ~VS18_1V8SUP;
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +0100569 } else {
570 val |= VS18_1V8SUP;
Faiz Abbasd2c05f52019-04-05 14:18:46 +0530571 val &= ~VS33_3V3SUP;
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +0100572 }
573
574 writel(val, &mmc_base->capa);
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +0100575
576 return val;
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +0100577}
Jean-Jacques Hiblot14761ca2018-01-30 16:01:35 +0100578
579#ifdef MMC_SUPPORTS_TUNING
580static void omap_hsmmc_disable_tuning(struct mmc *mmc)
581{
582 struct hsmmc *mmc_base;
583 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
584 u32 val;
585
586 mmc_base = priv->base_addr;
587 val = readl(&mmc_base->ac12);
588 val &= ~(AC12_SCLK_SEL);
589 writel(val, &mmc_base->ac12);
590
591 val = readl(&mmc_base->dll);
592 val &= ~(DLL_FORCE_VALUE | DLL_SWT);
593 writel(val, &mmc_base->dll);
594}
595
596static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
597{
598 int i;
599 struct hsmmc *mmc_base;
600 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
601 u32 val;
602
603 mmc_base = priv->base_addr;
604 val = readl(&mmc_base->dll);
605 val |= DLL_FORCE_VALUE;
606 val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
607 val |= (count << DLL_FORCE_SR_C_SHIFT);
608 writel(val, &mmc_base->dll);
609
610 val |= DLL_CALIB;
611 writel(val, &mmc_base->dll);
612 for (i = 0; i < 1000; i++) {
613 if (readl(&mmc_base->dll) & DLL_CALIB)
614 break;
615 }
616 val &= ~DLL_CALIB;
617 writel(val, &mmc_base->dll);
618}
619
620static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
621{
622 struct omap_hsmmc_data *priv = dev_get_priv(dev);
623 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
624 struct mmc *mmc = upriv->mmc;
625 struct hsmmc *mmc_base;
626 u32 val;
627 u8 cur_match, prev_match = 0;
628 int ret;
629 u32 phase_delay = 0;
630 u32 start_window = 0, max_window = 0;
631 u32 length = 0, max_len = 0;
Faiz Abbas351a4aa2019-01-30 18:08:42 +0530632 bool single_point_failure = false;
633 struct udevice *thermal_dev;
634 int temperature;
635 int i;
Jean-Jacques Hiblot14761ca2018-01-30 16:01:35 +0100636
637 mmc_base = priv->base_addr;
638 val = readl(&mmc_base->capa2);
639
640 /* clock tuning is not needed for upto 52MHz */
641 if (!((mmc->selected_mode == MMC_HS_200) ||
642 (mmc->selected_mode == UHS_SDR104) ||
643 ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
644 return 0;
645
Faiz Abbas351a4aa2019-01-30 18:08:42 +0530646 ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
647 if (ret) {
648 printf("Couldn't get thermal device for tuning\n");
649 return ret;
650 }
651 ret = thermal_get_temp(thermal_dev, &temperature);
652 if (ret) {
653 printf("Couldn't get temperature for tuning\n");
654 return ret;
655 }
Jean-Jacques Hiblot14761ca2018-01-30 16:01:35 +0100656 val = readl(&mmc_base->dll);
657 val |= DLL_SWT;
658 writel(val, &mmc_base->dll);
Faiz Abbas351a4aa2019-01-30 18:08:42 +0530659
660 /*
661 * Stage 1: Search for a maximum pass window ignoring any
662 * any single point failures. If the tuning value ends up
663 * near it, move away from it in stage 2 below
664 */
Jean-Jacques Hiblot14761ca2018-01-30 16:01:35 +0100665 while (phase_delay <= MAX_PHASE_DELAY) {
666 omap_hsmmc_set_dll(mmc, phase_delay);
667
668 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
669
670 if (cur_match) {
671 if (prev_match) {
672 length++;
Faiz Abbas351a4aa2019-01-30 18:08:42 +0530673 } else if (single_point_failure) {
674 /* ignore single point failure */
675 length++;
676 single_point_failure = false;
Jean-Jacques Hiblot14761ca2018-01-30 16:01:35 +0100677 } else {
678 start_window = phase_delay;
679 length = 1;
680 }
Faiz Abbas351a4aa2019-01-30 18:08:42 +0530681 } else {
682 single_point_failure = prev_match;
Jean-Jacques Hiblot14761ca2018-01-30 16:01:35 +0100683 }
684
685 if (length > max_len) {
686 max_window = start_window;
687 max_len = length;
688 }
689
690 prev_match = cur_match;
691 phase_delay += 4;
692 }
693
694 if (!max_len) {
695 ret = -EIO;
696 goto tuning_error;
697 }
698
699 val = readl(&mmc_base->ac12);
700 if (!(val & AC12_SCLK_SEL)) {
701 ret = -EIO;
702 goto tuning_error;
703 }
Faiz Abbas351a4aa2019-01-30 18:08:42 +0530704 /*
705 * Assign tuning value as a ratio of maximum pass window based
706 * on temperature
707 */
708 if (temperature < -20000)
709 phase_delay = min(max_window + 4 * max_len - 24,
710 max_window +
711 DIV_ROUND_UP(13 * max_len, 16) * 4);
712 else if (temperature < 20000)
713 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
714 else if (temperature < 40000)
715 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
716 else if (temperature < 70000)
717 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
718 else if (temperature < 90000)
719 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
720 else if (temperature < 120000)
721 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
722 else
723 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
Jean-Jacques Hiblot14761ca2018-01-30 16:01:35 +0100724
Faiz Abbas351a4aa2019-01-30 18:08:42 +0530725 /*
726 * Stage 2: Search for a single point failure near the chosen tuning
727 * value in two steps. First in the +3 to +10 range and then in the
728 * +2 to -10 range. If found, move away from it in the appropriate
729 * direction by the appropriate amount depending on the temperature.
730 */
731 for (i = 3; i <= 10; i++) {
732 omap_hsmmc_set_dll(mmc, phase_delay + i);
733 if (mmc_send_tuning(mmc, opcode, NULL)) {
734 if (temperature < 10000)
735 phase_delay += i + 6;
736 else if (temperature < 20000)
737 phase_delay += i - 12;
738 else if (temperature < 70000)
739 phase_delay += i - 8;
740 else if (temperature < 90000)
741 phase_delay += i - 6;
742 else
743 phase_delay += i - 6;
744
745 goto single_failure_found;
746 }
747 }
748
749 for (i = 2; i >= -10; i--) {
750 omap_hsmmc_set_dll(mmc, phase_delay + i);
751 if (mmc_send_tuning(mmc, opcode, NULL)) {
752 if (temperature < 10000)
753 phase_delay += i + 12;
754 else if (temperature < 20000)
755 phase_delay += i + 8;
756 else if (temperature < 70000)
757 phase_delay += i + 8;
758 else if (temperature < 90000)
759 phase_delay += i + 10;
760 else
761 phase_delay += i + 12;
762
763 goto single_failure_found;
764 }
765 }
766
767single_failure_found:
768
Jean-Jacques Hiblot14761ca2018-01-30 16:01:35 +0100769 omap_hsmmc_set_dll(mmc, phase_delay);
770
771 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
772 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
773
774 return 0;
775
776tuning_error:
777
778 omap_hsmmc_disable_tuning(mmc);
779 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
780 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
781
782 return ret;
783}
784#endif
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +0100785#endif
786
Jean-Jacques Hiblot2faa1a32018-01-30 16:01:36 +0100787static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
788{
789 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
790 struct hsmmc *mmc_base = priv->base_addr;
791 u32 irq_mask = INT_EN_MASK;
792
793 /*
794 * TODO: Errata i802 indicates only DCRC interrupts can occur during
795 * tuning procedure and DCRC should be disabled. But see occurences
796 * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
797 * interrupts occur along with BRR, so the data is actually in the
798 * buffer. It has to be debugged why these interrutps occur
799 */
800 if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
801 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
802
803 writel(irq_mask, &mmc_base->ie);
804}
805
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200806static int omap_hsmmc_init_setup(struct mmc *mmc)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700807{
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +0100808 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +0000809 struct hsmmc *mmc_base;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700810 unsigned int reg_val;
811 unsigned int dsor;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500812 ulong start;
Sukumar Ghoraide941242010-09-18 20:32:33 -0700813
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +0100814 mmc_base = priv->base_addr;
Balaji T K14fa2dd2011-09-08 06:34:57 +0000815 mmc_board_init(mmc);
Sukumar Ghoraide941242010-09-18 20:32:33 -0700816
817 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
818 &mmc_base->sysconfig);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500819 start = get_timer(0);
820 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
821 if (get_timer(0) - start > MAX_RETRY_MS) {
822 printf("%s: timedout waiting for cc2!\n", __func__);
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900823 return -ETIMEDOUT;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500824 }
825 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700826 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500827 start = get_timer(0);
828 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
829 if (get_timer(0) - start > MAX_RETRY_MS) {
830 printf("%s: timedout waiting for softresetall!\n",
831 __func__);
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900832 return -ETIMEDOUT;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500833 }
834 }
Jean-Jacques Hiblot27a4b3b2018-02-23 10:40:18 +0100835#ifdef CONFIG_MMC_OMAP_HS_ADMA
Kishon Vijay Abraham If0d53e82017-09-21 16:51:34 +0200836 reg_val = readl(&mmc_base->hl_hwinfo);
837 if (reg_val & MADMA_EN)
838 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
839#endif
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +0100840
841#if CONFIG_IS_ENABLED(DM_MMC)
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +0100842 reg_val = omap_hsmmc_set_capabilities(mmc);
Faiz Abbasd2c05f52019-04-05 14:18:46 +0530843 omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +0100844 MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +0100845#else
Pali Rohár82c829d2020-07-03 22:58:23 +0200846 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V3, &mmc_base->hctl);
Faiz Abbasd2c05f52019-04-05 14:18:46 +0530847 writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
Sukumar Ghoraide941242010-09-18 20:32:33 -0700848 &mmc_base->capa);
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +0100849#endif
Sukumar Ghoraide941242010-09-18 20:32:33 -0700850
851 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
852
853 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
854 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
855 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
856
857 dsor = 240;
858 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
Kishon Vijay Abraham I29171dc2017-09-21 16:51:36 +0200859 (ICE_STOP | DTO_15THDTO));
Sukumar Ghoraide941242010-09-18 20:32:33 -0700860 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
861 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500862 start = get_timer(0);
863 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
864 if (get_timer(0) - start > MAX_RETRY_MS) {
865 printf("%s: timedout waiting for ics!\n", __func__);
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900866 return -ETIMEDOUT;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -0500867 }
868 }
Sukumar Ghoraide941242010-09-18 20:32:33 -0700869 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
870
871 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
872
Jean-Jacques Hiblot2faa1a32018-01-30 16:01:36 +0100873 mmc_enable_irq(mmc, NULL);
Jean-Jacques Hiblot42182c92018-01-30 16:01:44 +0100874
875#if !CONFIG_IS_ENABLED(DM_MMC)
Sukumar Ghoraide941242010-09-18 20:32:33 -0700876 mmc_init_stream(mmc_base);
Jean-Jacques Hiblot42182c92018-01-30 16:01:44 +0100877#endif
Sukumar Ghoraide941242010-09-18 20:32:33 -0700878
879 return 0;
880}
881
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +0000882/*
883 * MMC controller internal finite state machine reset
884 *
885 * Used to reset command or data internal state machines, using respectively
886 * SRC or SRD bit of SYSCTL register
887 */
888static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
889{
890 ulong start;
891
892 mmc_reg_out(&mmc_base->sysctl, bit, bit);
893
Oleksandr Tyshchenko61a6cc22013-08-06 13:44:16 +0300894 /*
895 * CMD(DAT) lines reset procedures are slightly different
896 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
897 * According to OMAP3 TRM:
898 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
899 * returns to 0x0.
900 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
901 * procedure steps must be as follows:
902 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
903 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
904 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
905 * 3. Wait until the SRC (SRD) bit returns to 0x0
906 * (reset procedure is completed).
907 */
908#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
Nikita Kiryanovdce55b92015-07-30 23:56:20 +0300909 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
Oleksandr Tyshchenko61a6cc22013-08-06 13:44:16 +0300910 if (!(readl(&mmc_base->sysctl) & bit)) {
911 start = get_timer(0);
912 while (!(readl(&mmc_base->sysctl) & bit)) {
Jean-Jacques Hiblota4efd732018-01-30 16:01:37 +0100913 if (get_timer(0) - start > MMC_TIMEOUT_MS)
Oleksandr Tyshchenko61a6cc22013-08-06 13:44:16 +0300914 return;
915 }
916 }
917#endif
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +0000918 start = get_timer(0);
919 while ((readl(&mmc_base->sysctl) & bit) != 0) {
920 if (get_timer(0) - start > MAX_RETRY_MS) {
921 printf("%s: timedout waiting for sysctl %x to clear\n",
922 __func__, bit);
923 return;
924 }
925 }
926}
Kishon Vijay Abraham If0d53e82017-09-21 16:51:34 +0200927
Jean-Jacques Hiblot27a4b3b2018-02-23 10:40:18 +0100928#ifdef CONFIG_MMC_OMAP_HS_ADMA
Kishon Vijay Abraham If0d53e82017-09-21 16:51:34 +0200929static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
930{
931 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
932 struct omap_hsmmc_adma_desc *desc;
933 u8 attr;
934
935 desc = &priv->adma_desc_table[priv->desc_slot];
936
937 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
938 if (!end)
939 priv->desc_slot++;
940 else
941 attr |= ADMA_DESC_ATTR_END;
942
943 desc->len = len;
944 desc->addr = (u32)buf;
945 desc->reserved = 0;
946 desc->attr = attr;
947}
948
949static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
950 struct mmc_data *data)
951{
952 uint total_len = data->blocksize * data->blocks;
953 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
954 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
955 int i = desc_count;
956 char *buf;
957
958 priv->desc_slot = 0;
959 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
960 memalign(ARCH_DMA_MINALIGN, desc_count *
961 sizeof(struct omap_hsmmc_adma_desc));
962
963 if (data->flags & MMC_DATA_READ)
964 buf = data->dest;
965 else
966 buf = (char *)data->src;
967
968 while (--i) {
969 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
970 buf += ADMA_MAX_LEN;
971 total_len -= ADMA_MAX_LEN;
972 }
973
974 omap_hsmmc_adma_desc(mmc, buf, total_len, true);
975
976 flush_dcache_range((long)priv->adma_desc_table,
977 (long)priv->adma_desc_table +
978 ROUND(desc_count *
979 sizeof(struct omap_hsmmc_adma_desc),
980 ARCH_DMA_MINALIGN));
981}
982
983static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
984{
985 struct hsmmc *mmc_base;
986 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
987 u32 val;
988 char *buf;
989
990 mmc_base = priv->base_addr;
991 omap_hsmmc_prepare_adma_table(mmc, data);
992
993 if (data->flags & MMC_DATA_READ)
994 buf = data->dest;
995 else
996 buf = (char *)data->src;
997
998 val = readl(&mmc_base->hctl);
999 val |= DMA_SELECT;
1000 writel(val, &mmc_base->hctl);
1001
1002 val = readl(&mmc_base->con);
1003 val |= DMA_MASTER;
1004 writel(val, &mmc_base->con);
1005
1006 writel((u32)priv->adma_desc_table, &mmc_base->admasal);
1007
1008 flush_dcache_range((u32)buf,
1009 (u32)buf +
1010 ROUND(data->blocksize * data->blocks,
1011 ARCH_DMA_MINALIGN));
1012}
1013
1014static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
1015{
1016 struct hsmmc *mmc_base;
1017 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1018 u32 val;
1019
1020 mmc_base = priv->base_addr;
1021
1022 val = readl(&mmc_base->con);
1023 val &= ~DMA_MASTER;
1024 writel(val, &mmc_base->con);
1025
1026 val = readl(&mmc_base->hctl);
1027 val &= ~DMA_SELECT;
1028 writel(val, &mmc_base->hctl);
1029
1030 kfree(priv->adma_desc_table);
1031}
1032#else
1033#define omap_hsmmc_adma_desc
1034#define omap_hsmmc_prepare_adma_table
1035#define omap_hsmmc_prepare_data
1036#define omap_hsmmc_dma_cleanup
1037#endif
1038
Simon Glassc4d660d2017-07-04 13:31:19 -06001039#if !CONFIG_IS_ENABLED(DM_MMC)
Pantelis Antoniouab769f22014-02-26 19:28:45 +02001040static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
Sukumar Ghoraide941242010-09-18 20:32:33 -07001041 struct mmc_data *data)
1042{
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +01001043 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
Jean-Jacques Hiblotb5511d62017-04-14 19:50:02 +02001044#else
1045static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1046 struct mmc_data *data)
1047{
1048 struct omap_hsmmc_data *priv = dev_get_priv(dev);
Kishon Vijay Abraham If0d53e82017-09-21 16:51:34 +02001049 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1050 struct mmc *mmc = upriv->mmc;
1051#endif
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +00001052 struct hsmmc *mmc_base;
Sukumar Ghoraide941242010-09-18 20:32:33 -07001053 unsigned int flags, mmc_stat;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -05001054 ulong start;
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +01001055 priv->last_cmd = cmd->cmdidx;
Sukumar Ghoraide941242010-09-18 20:32:33 -07001056
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +01001057 mmc_base = priv->base_addr;
Kishon Vijay Abraham I866bb982017-09-21 16:51:35 +02001058
1059 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
1060 return 0;
1061
Nishanth Menoneb9a28f2010-11-19 11:18:12 -05001062 start = get_timer(0);
Tom Rinia7778f82012-01-30 11:22:25 +00001063 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
Nishanth Menoneb9a28f2010-11-19 11:18:12 -05001064 if (get_timer(0) - start > MAX_RETRY_MS) {
Tom Rinia7778f82012-01-30 11:22:25 +00001065 printf("%s: timedout waiting on cmd inhibit to clear\n",
1066 __func__);
Jean-Jacques Hiblotb2ffa332019-07-02 10:53:48 +02001067 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1068 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
Jaehoon Chung915ffa52016-07-19 16:33:36 +09001069 return -ETIMEDOUT;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -05001070 }
1071 }
Sukumar Ghoraide941242010-09-18 20:32:33 -07001072 writel(0xFFFFFFFF, &mmc_base->stat);
Jean-Jacques Hiblotb2ffa332019-07-02 10:53:48 +02001073 if (readl(&mmc_base->stat)) {
1074 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1075 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -05001076 }
Jean-Jacques Hiblotb2ffa332019-07-02 10:53:48 +02001077
Sukumar Ghoraide941242010-09-18 20:32:33 -07001078 /*
1079 * CMDREG
1080 * CMDIDX[13:8] : Command index
1081 * DATAPRNT[5] : Data Present Select
1082 * ENCMDIDX[4] : Command Index Check Enable
1083 * ENCMDCRC[3] : Command CRC Check Enable
1084 * RSPTYP[1:0]
1085 * 00 = No Response
1086 * 01 = Length 136
1087 * 10 = Length 48
1088 * 11 = Length 48 Check busy after response
1089 */
1090 /* Delay added before checking the status of frq change
1091 * retry not supported by mmc.c(core file)
1092 */
1093 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1094 udelay(50000); /* wait 50 ms */
1095
1096 if (!(cmd->resp_type & MMC_RSP_PRESENT))
1097 flags = 0;
1098 else if (cmd->resp_type & MMC_RSP_136)
1099 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1100 else if (cmd->resp_type & MMC_RSP_BUSY)
1101 flags = RSP_TYPE_LGHT48B;
1102 else
1103 flags = RSP_TYPE_LGHT48;
1104
1105 /* enable default flags */
1106 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
Kishon Vijay Abraham I29171dc2017-09-21 16:51:36 +02001107 MSBS_SGLEBLK);
1108 flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
Sukumar Ghoraide941242010-09-18 20:32:33 -07001109
1110 if (cmd->resp_type & MMC_RSP_CRC)
1111 flags |= CCCE_CHECK;
1112 if (cmd->resp_type & MMC_RSP_OPCODE)
1113 flags |= CICE_CHECK;
1114
1115 if (data) {
1116 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1117 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
Kishon Vijay Abraham I866bb982017-09-21 16:51:35 +02001118 flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
Sukumar Ghoraide941242010-09-18 20:32:33 -07001119 data->blocksize = 512;
1120 writel(data->blocksize | (data->blocks << 16),
1121 &mmc_base->blk);
1122 } else
1123 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1124
1125 if (data->flags & MMC_DATA_READ)
1126 flags |= (DP_DATA | DDIR_READ);
1127 else
1128 flags |= (DP_DATA | DDIR_WRITE);
Kishon Vijay Abraham If0d53e82017-09-21 16:51:34 +02001129
Jean-Jacques Hiblot27a4b3b2018-02-23 10:40:18 +01001130#ifdef CONFIG_MMC_OMAP_HS_ADMA
Kishon Vijay Abraham If0d53e82017-09-21 16:51:34 +02001131 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1132 !mmc_is_tuning_cmd(cmd->cmdidx)) {
1133 omap_hsmmc_prepare_data(mmc, data);
1134 flags |= DE_ENABLE;
1135 }
1136#endif
Sukumar Ghoraide941242010-09-18 20:32:33 -07001137 }
1138
Jean-Jacques Hiblot2faa1a32018-01-30 16:01:36 +01001139 mmc_enable_irq(mmc, cmd);
1140
Sukumar Ghoraide941242010-09-18 20:32:33 -07001141 writel(cmd->cmdarg, &mmc_base->arg);
Lubomir Popov152ba362013-08-14 18:59:18 +03001142 udelay(20); /* To fix "No status update" error on eMMC */
Sukumar Ghoraide941242010-09-18 20:32:33 -07001143 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1144
Nishanth Menoneb9a28f2010-11-19 11:18:12 -05001145 start = get_timer(0);
Sukumar Ghoraide941242010-09-18 20:32:33 -07001146 do {
1147 mmc_stat = readl(&mmc_base->stat);
Kishon Vijay Abraham If0d53e82017-09-21 16:51:34 +02001148 if (get_timer(start) > MAX_RETRY_MS) {
Nishanth Menoneb9a28f2010-11-19 11:18:12 -05001149 printf("%s : timeout: No status update\n", __func__);
Jaehoon Chung915ffa52016-07-19 16:33:36 +09001150 return -ETIMEDOUT;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -05001151 }
1152 } while (!mmc_stat);
Sukumar Ghoraide941242010-09-18 20:32:33 -07001153
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +00001154 if ((mmc_stat & IE_CTO) != 0) {
1155 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
Jaehoon Chung915ffa52016-07-19 16:33:36 +09001156 return -ETIMEDOUT;
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +00001157 } else if ((mmc_stat & ERRI_MASK) != 0)
Sukumar Ghoraide941242010-09-18 20:32:33 -07001158 return -1;
1159
1160 if (mmc_stat & CC_MASK) {
1161 writel(CC_MASK, &mmc_base->stat);
1162 if (cmd->resp_type & MMC_RSP_PRESENT) {
1163 if (cmd->resp_type & MMC_RSP_136) {
1164 /* response type 2 */
1165 cmd->response[3] = readl(&mmc_base->rsp10);
1166 cmd->response[2] = readl(&mmc_base->rsp32);
1167 cmd->response[1] = readl(&mmc_base->rsp54);
1168 cmd->response[0] = readl(&mmc_base->rsp76);
1169 } else
1170 /* response types 1, 1b, 3, 4, 5, 6 */
1171 cmd->response[0] = readl(&mmc_base->rsp10);
1172 }
1173 }
1174
Jean-Jacques Hiblot27a4b3b2018-02-23 10:40:18 +01001175#ifdef CONFIG_MMC_OMAP_HS_ADMA
Kishon Vijay Abraham If0d53e82017-09-21 16:51:34 +02001176 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1177 !mmc_is_tuning_cmd(cmd->cmdidx)) {
1178 u32 sz_mb, timeout;
1179
1180 if (mmc_stat & IE_ADMAE) {
1181 omap_hsmmc_dma_cleanup(mmc);
1182 return -EIO;
1183 }
1184
1185 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
1186 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1187 if (timeout < MAX_RETRY_MS)
1188 timeout = MAX_RETRY_MS;
1189
1190 start = get_timer(0);
1191 do {
1192 mmc_stat = readl(&mmc_base->stat);
1193 if (mmc_stat & TC_MASK) {
1194 writel(readl(&mmc_base->stat) | TC_MASK,
1195 &mmc_base->stat);
1196 break;
1197 }
1198 if (get_timer(start) > timeout) {
1199 printf("%s : DMA timeout: No status update\n",
1200 __func__);
1201 return -ETIMEDOUT;
1202 }
1203 } while (1);
1204
1205 omap_hsmmc_dma_cleanup(mmc);
1206 return 0;
1207 }
1208#endif
1209
Sukumar Ghoraide941242010-09-18 20:32:33 -07001210 if (data && (data->flags & MMC_DATA_READ)) {
1211 mmc_read_data(mmc_base, data->dest,
1212 data->blocksize * data->blocks);
1213 } else if (data && (data->flags & MMC_DATA_WRITE)) {
1214 mmc_write_data(mmc_base, data->src,
1215 data->blocksize * data->blocks);
1216 }
1217 return 0;
1218}
1219
Sricharan933efe62011-11-15 09:49:53 -05001220static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
Sukumar Ghoraide941242010-09-18 20:32:33 -07001221{
1222 unsigned int *output_buf = (unsigned int *)buf;
1223 unsigned int mmc_stat;
1224 unsigned int count;
1225
1226 /*
1227 * Start Polled Read
1228 */
1229 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1230 count /= 4;
1231
1232 while (size) {
Nishanth Menoneb9a28f2010-11-19 11:18:12 -05001233 ulong start = get_timer(0);
Sukumar Ghoraide941242010-09-18 20:32:33 -07001234 do {
1235 mmc_stat = readl(&mmc_base->stat);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -05001236 if (get_timer(0) - start > MAX_RETRY_MS) {
1237 printf("%s: timedout waiting for status!\n",
1238 __func__);
Jaehoon Chung915ffa52016-07-19 16:33:36 +09001239 return -ETIMEDOUT;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -05001240 }
Sukumar Ghoraide941242010-09-18 20:32:33 -07001241 } while (mmc_stat == 0);
1242
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +00001243 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1244 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1245
Sukumar Ghoraide941242010-09-18 20:32:33 -07001246 if ((mmc_stat & ERRI_MASK) != 0)
1247 return 1;
1248
1249 if (mmc_stat & BRR_MASK) {
1250 unsigned int k;
1251
1252 writel(readl(&mmc_base->stat) | BRR_MASK,
1253 &mmc_base->stat);
1254 for (k = 0; k < count; k++) {
1255 *output_buf = readl(&mmc_base->data);
1256 output_buf++;
1257 }
1258 size -= (count*4);
1259 }
1260
1261 if (mmc_stat & BWR_MASK)
1262 writel(readl(&mmc_base->stat) | BWR_MASK,
1263 &mmc_base->stat);
1264
1265 if (mmc_stat & TC_MASK) {
1266 writel(readl(&mmc_base->stat) | TC_MASK,
1267 &mmc_base->stat);
1268 break;
1269 }
1270 }
1271 return 0;
1272}
1273
Jean-Jacques Hiblotc7d08d82018-02-23 10:40:17 +01001274#if CONFIG_IS_ENABLED(MMC_WRITE)
Sricharan933efe62011-11-15 09:49:53 -05001275static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
Jean-Jacques Hiblotc7d08d82018-02-23 10:40:17 +01001276 unsigned int size)
Sukumar Ghoraide941242010-09-18 20:32:33 -07001277{
1278 unsigned int *input_buf = (unsigned int *)buf;
1279 unsigned int mmc_stat;
1280 unsigned int count;
1281
1282 /*
Lubomir Popov152ba362013-08-14 18:59:18 +03001283 * Start Polled Write
Sukumar Ghoraide941242010-09-18 20:32:33 -07001284 */
1285 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1286 count /= 4;
1287
1288 while (size) {
Nishanth Menoneb9a28f2010-11-19 11:18:12 -05001289 ulong start = get_timer(0);
Sukumar Ghoraide941242010-09-18 20:32:33 -07001290 do {
1291 mmc_stat = readl(&mmc_base->stat);
Nishanth Menoneb9a28f2010-11-19 11:18:12 -05001292 if (get_timer(0) - start > MAX_RETRY_MS) {
1293 printf("%s: timedout waiting for status!\n",
1294 __func__);
Jaehoon Chung915ffa52016-07-19 16:33:36 +09001295 return -ETIMEDOUT;
Nishanth Menoneb9a28f2010-11-19 11:18:12 -05001296 }
Sukumar Ghoraide941242010-09-18 20:32:33 -07001297 } while (mmc_stat == 0);
1298
Grazvydas Ignotas25c719e2012-03-19 12:12:06 +00001299 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1300 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1301
Sukumar Ghoraide941242010-09-18 20:32:33 -07001302 if ((mmc_stat & ERRI_MASK) != 0)
1303 return 1;
1304
1305 if (mmc_stat & BWR_MASK) {
1306 unsigned int k;
1307
1308 writel(readl(&mmc_base->stat) | BWR_MASK,
1309 &mmc_base->stat);
1310 for (k = 0; k < count; k++) {
1311 writel(*input_buf, &mmc_base->data);
1312 input_buf++;
1313 }
1314 size -= (count*4);
1315 }
1316
1317 if (mmc_stat & BRR_MASK)
1318 writel(readl(&mmc_base->stat) | BRR_MASK,
1319 &mmc_base->stat);
1320
1321 if (mmc_stat & TC_MASK) {
1322 writel(readl(&mmc_base->stat) | TC_MASK,
1323 &mmc_base->stat);
1324 break;
1325 }
1326 }
1327 return 0;
1328}
Jean-Jacques Hiblotc7d08d82018-02-23 10:40:17 +01001329#else
1330static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1331 unsigned int size)
1332{
1333 return -ENOTSUPP;
1334}
1335#endif
Jean-Jacques Hiblot5baf5432018-01-30 16:01:30 +01001336static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1337{
1338 writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1339}
1340
1341static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1342{
1343 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1344}
1345
1346static void omap_hsmmc_set_clock(struct mmc *mmc)
1347{
1348 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1349 struct hsmmc *mmc_base;
1350 unsigned int dsor = 0;
1351 ulong start;
1352
1353 mmc_base = priv->base_addr;
1354 omap_hsmmc_stop_clock(mmc_base);
1355
1356 /* TODO: Is setting DTO required here? */
1357 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1358 (ICE_STOP | DTO_15THDTO));
1359
1360 if (mmc->clock != 0) {
1361 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1362 if (dsor > CLKD_MAX)
1363 dsor = CLKD_MAX;
1364 } else {
1365 dsor = CLKD_MAX;
1366 }
1367
1368 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1369 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1370
1371 start = get_timer(0);
1372 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1373 if (get_timer(0) - start > MAX_RETRY_MS) {
1374 printf("%s: timedout waiting for ics!\n", __func__);
1375 return;
1376 }
1377 }
1378
Jean-Jacques Hiblot3149c132018-01-30 16:01:43 +01001379 priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1380 mmc->clock = priv->clock;
Jean-Jacques Hiblot5baf5432018-01-30 16:01:30 +01001381 omap_hsmmc_start_clock(mmc_base);
1382}
1383
Kishon Vijay Abraham I48a2f112018-01-30 16:01:31 +01001384static void omap_hsmmc_set_bus_width(struct mmc *mmc)
Sukumar Ghoraide941242010-09-18 20:32:33 -07001385{
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +01001386 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
Nikita Kiryanovcc22b0c2012-12-03 02:19:43 +00001387 struct hsmmc *mmc_base;
Sukumar Ghoraide941242010-09-18 20:32:33 -07001388
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +01001389 mmc_base = priv->base_addr;
Sukumar Ghoraide941242010-09-18 20:32:33 -07001390 /* configue bus width */
1391 switch (mmc->bus_width) {
1392 case 8:
1393 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1394 &mmc_base->con);
1395 break;
1396
1397 case 4:
1398 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1399 &mmc_base->con);
1400 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1401 &mmc_base->hctl);
1402 break;
1403
1404 case 1:
1405 default:
1406 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1407 &mmc_base->con);
1408 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1409 &mmc_base->hctl);
1410 break;
1411 }
1412
Kishon Vijay Abraham I48a2f112018-01-30 16:01:31 +01001413 priv->bus_width = mmc->bus_width;
1414}
1415
1416#if !CONFIG_IS_ENABLED(DM_MMC)
1417static int omap_hsmmc_set_ios(struct mmc *mmc)
1418{
1419 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1420#else
1421static int omap_hsmmc_set_ios(struct udevice *dev)
1422{
1423 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1424 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1425 struct mmc *mmc = upriv->mmc;
1426#endif
Kishon Vijay Abraham I90321dc2018-01-30 16:01:45 +01001427 struct hsmmc *mmc_base = priv->base_addr;
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +01001428 int ret = 0;
Kishon Vijay Abraham I48a2f112018-01-30 16:01:31 +01001429
1430 if (priv->bus_width != mmc->bus_width)
1431 omap_hsmmc_set_bus_width(mmc);
1432
Jean-Jacques Hiblot5baf5432018-01-30 16:01:30 +01001433 if (priv->clock != mmc->clock)
1434 omap_hsmmc_set_clock(mmc);
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +09001435
Kishon Vijay Abraham I90321dc2018-01-30 16:01:45 +01001436 if (mmc->clk_disable)
1437 omap_hsmmc_stop_clock(mmc_base);
1438 else
1439 omap_hsmmc_start_clock(mmc_base);
1440
Jean-Jacques Hiblot8fc238b2018-01-30 16:01:33 +01001441#if CONFIG_IS_ENABLED(DM_MMC)
1442 if (priv->mode != mmc->selected_mode)
1443 omap_hsmmc_set_timing(mmc);
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +01001444
1445#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1446 if (priv->signal_voltage != mmc->signal_voltage)
1447 ret = omap_hsmmc_set_signal_voltage(mmc);
Jean-Jacques Hiblot8fc238b2018-01-30 16:01:33 +01001448#endif
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +01001449#endif
1450 return ret;
Sukumar Ghoraide941242010-09-18 20:32:33 -07001451}
1452
Pantelis Antoniouab769f22014-02-26 19:28:45 +02001453#ifdef OMAP_HSMMC_USE_GPIO
Simon Glassc4d660d2017-07-04 13:31:19 -06001454#if CONFIG_IS_ENABLED(DM_MMC)
Jean-Jacques Hiblotb5511d62017-04-14 19:50:02 +02001455static int omap_hsmmc_getcd(struct udevice *dev)
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301456{
Adam Ford307a2142018-08-21 07:16:56 -05001457 int value = -1;
1458#if CONFIG_IS_ENABLED(DM_GPIO)
Adam Fordf4df4052018-09-08 08:16:23 -05001459 struct omap_hsmmc_data *priv = dev_get_priv(dev);
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301460 value = dm_gpio_get_value(&priv->cd_gpio);
Adam Ford307a2142018-08-21 07:16:56 -05001461#endif
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301462 /* if no CD return as 1 */
1463 if (value < 0)
1464 return 1;
1465
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301466 return value;
1467}
1468
Jean-Jacques Hiblotb5511d62017-04-14 19:50:02 +02001469static int omap_hsmmc_getwp(struct udevice *dev)
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301470{
Adam Ford307a2142018-08-21 07:16:56 -05001471 int value = 0;
1472#if CONFIG_IS_ENABLED(DM_GPIO)
Jean-Jacques Hiblotb5511d62017-04-14 19:50:02 +02001473 struct omap_hsmmc_data *priv = dev_get_priv(dev);
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301474 value = dm_gpio_get_value(&priv->wp_gpio);
Adam Ford307a2142018-08-21 07:16:56 -05001475#endif
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301476 /* if no WP return as 0 */
1477 if (value < 0)
1478 return 0;
1479 return value;
1480}
1481#else
Pantelis Antoniouab769f22014-02-26 19:28:45 +02001482static int omap_hsmmc_getcd(struct mmc *mmc)
1483{
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +01001484 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
Pantelis Antoniouab769f22014-02-26 19:28:45 +02001485 int cd_gpio;
1486
1487 /* if no CD return as 1 */
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +01001488 cd_gpio = priv->cd_gpio;
Pantelis Antoniouab769f22014-02-26 19:28:45 +02001489 if (cd_gpio < 0)
1490 return 1;
1491
Igor Grinberg0b03a932014-11-03 11:32:23 +02001492 /* NOTE: assumes card detect signal is active-low */
1493 return !gpio_get_value(cd_gpio);
Pantelis Antoniouab769f22014-02-26 19:28:45 +02001494}
1495
1496static int omap_hsmmc_getwp(struct mmc *mmc)
1497{
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +01001498 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
Pantelis Antoniouab769f22014-02-26 19:28:45 +02001499 int wp_gpio;
1500
1501 /* if no WP return as 0 */
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +01001502 wp_gpio = priv->wp_gpio;
Pantelis Antoniouab769f22014-02-26 19:28:45 +02001503 if (wp_gpio < 0)
1504 return 0;
1505
Igor Grinberg0b03a932014-11-03 11:32:23 +02001506 /* NOTE: assumes write protect signal is active-high */
Pantelis Antoniouab769f22014-02-26 19:28:45 +02001507 return gpio_get_value(wp_gpio);
1508}
1509#endif
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301510#endif
Pantelis Antoniouab769f22014-02-26 19:28:45 +02001511
Simon Glassc4d660d2017-07-04 13:31:19 -06001512#if CONFIG_IS_ENABLED(DM_MMC)
Jean-Jacques Hiblotb5511d62017-04-14 19:50:02 +02001513static const struct dm_mmc_ops omap_hsmmc_ops = {
1514 .send_cmd = omap_hsmmc_send_cmd,
1515 .set_ios = omap_hsmmc_set_ios,
1516#ifdef OMAP_HSMMC_USE_GPIO
1517 .get_cd = omap_hsmmc_getcd,
1518 .get_wp = omap_hsmmc_getwp,
1519#endif
Jean-Jacques Hiblot14761ca2018-01-30 16:01:35 +01001520#ifdef MMC_SUPPORTS_TUNING
1521 .execute_tuning = omap_hsmmc_execute_tuning,
1522#endif
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +01001523 .wait_dat0 = omap_hsmmc_wait_dat0,
Jean-Jacques Hiblotb5511d62017-04-14 19:50:02 +02001524};
1525#else
Pantelis Antoniouab769f22014-02-26 19:28:45 +02001526static const struct mmc_ops omap_hsmmc_ops = {
1527 .send_cmd = omap_hsmmc_send_cmd,
1528 .set_ios = omap_hsmmc_set_ios,
1529 .init = omap_hsmmc_init_setup,
1530#ifdef OMAP_HSMMC_USE_GPIO
1531 .getcd = omap_hsmmc_getcd,
1532 .getwp = omap_hsmmc_getwp,
1533#endif
1534};
Jean-Jacques Hiblotb5511d62017-04-14 19:50:02 +02001535#endif
Pantelis Antoniouab769f22014-02-26 19:28:45 +02001536
Simon Glassc4d660d2017-07-04 13:31:19 -06001537#if !CONFIG_IS_ENABLED(DM_MMC)
Nikita Kiryanove3913f52012-12-03 02:19:47 +00001538int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1539 int wp_gpio)
Sukumar Ghoraide941242010-09-18 20:32:33 -07001540{
Pantelis Antoniou93bfd612014-03-11 19:34:20 +02001541 struct mmc *mmc;
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +01001542 struct omap_hsmmc_data *priv;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +02001543 struct mmc_config *cfg;
1544 uint host_caps_val;
Sukumar Ghoraide941242010-09-18 20:32:33 -07001545
Alex Kiernan4a41fec2018-02-09 15:24:38 +00001546 priv = calloc(1, sizeof(*priv));
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +01001547 if (priv == NULL)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +02001548 return -1;
1549
Rob Herring5a203972015-03-23 17:56:59 -05001550 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
Sukumar Ghoraide941242010-09-18 20:32:33 -07001551
1552 switch (dev_index) {
1553 case 0:
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +01001554 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
Sukumar Ghoraide941242010-09-18 20:32:33 -07001555 break;
Tom Rini1037d582011-10-12 06:20:50 +00001556#ifdef OMAP_HSMMC2_BASE
Sukumar Ghoraide941242010-09-18 20:32:33 -07001557 case 1:
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +01001558 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
Lubomir Popov152ba362013-08-14 18:59:18 +03001559#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
Nishanth Menon3891a542016-11-29 15:22:00 +05301560 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
Roger Quadros3b689392015-09-19 16:26:53 +05301561 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1562 defined(CONFIG_HSMMC2_8BIT)
Lubomir Popov152ba362013-08-14 18:59:18 +03001563 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1564 host_caps_val |= MMC_MODE_8BIT;
1565#endif
Sukumar Ghoraide941242010-09-18 20:32:33 -07001566 break;
Tom Rini1037d582011-10-12 06:20:50 +00001567#endif
1568#ifdef OMAP_HSMMC3_BASE
Sukumar Ghoraide941242010-09-18 20:32:33 -07001569 case 2:
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +01001570 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
Nishanth Menon3891a542016-11-29 15:22:00 +05301571#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
Lubomir Popov152ba362013-08-14 18:59:18 +03001572 /* Enable 8-bit interface for eMMC on DRA7XX */
1573 host_caps_val |= MMC_MODE_8BIT;
1574#endif
Sukumar Ghoraide941242010-09-18 20:32:33 -07001575 break;
Tom Rini1037d582011-10-12 06:20:50 +00001576#endif
Sukumar Ghoraide941242010-09-18 20:32:33 -07001577 default:
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +01001578 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
Sukumar Ghoraide941242010-09-18 20:32:33 -07001579 return 1;
1580 }
Pantelis Antoniouab769f22014-02-26 19:28:45 +02001581#ifdef OMAP_HSMMC_USE_GPIO
1582 /* on error gpio values are set to -1, which is what we want */
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +01001583 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1584 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
Pantelis Antoniouab769f22014-02-26 19:28:45 +02001585#endif
Peter Korsgaard173ddc52013-03-21 04:00:04 +00001586
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +01001587 cfg = &priv->cfg;
Sukumar Ghoraide941242010-09-18 20:32:33 -07001588
Pantelis Antoniou93bfd612014-03-11 19:34:20 +02001589 cfg->name = "OMAP SD/MMC";
1590 cfg->ops = &omap_hsmmc_ops;
1591
1592 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1593 cfg->host_caps = host_caps_val & ~host_caps_mask;
1594
1595 cfg->f_min = 400000;
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +00001596
1597 if (f_max != 0)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +02001598 cfg->f_max = f_max;
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +00001599 else {
Pantelis Antoniou93bfd612014-03-11 19:34:20 +02001600 if (cfg->host_caps & MMC_MODE_HS) {
1601 if (cfg->host_caps & MMC_MODE_HS_52MHz)
1602 cfg->f_max = 52000000;
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +00001603 else
Pantelis Antoniou93bfd612014-03-11 19:34:20 +02001604 cfg->f_max = 26000000;
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +00001605 } else
Pantelis Antoniou93bfd612014-03-11 19:34:20 +02001606 cfg->f_max = 20000000;
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +00001607 }
Sukumar Ghoraide941242010-09-18 20:32:33 -07001608
Pantelis Antoniou93bfd612014-03-11 19:34:20 +02001609 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
John Rigby8feafcc2011-04-18 05:50:08 +00001610
John Rigby4ca92442011-04-19 05:48:14 +00001611#if defined(CONFIG_OMAP34XX)
1612 /*
1613 * Silicon revs 2.1 and older do not support multiblock transfers.
1614 */
1615 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
Pantelis Antoniou93bfd612014-03-11 19:34:20 +02001616 cfg->b_max = 1;
John Rigby4ca92442011-04-19 05:48:14 +00001617#endif
Kishon Vijay Abraham I2d28eed2018-01-30 16:01:41 +01001618
Jean-Jacques Hiblotae000e22017-03-22 16:00:31 +01001619 mmc = mmc_create(cfg, priv);
Pantelis Antoniou93bfd612014-03-11 19:34:20 +02001620 if (mmc == NULL)
1621 return -1;
Sukumar Ghoraide941242010-09-18 20:32:33 -07001622
1623 return 0;
1624}
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301625#else
Kishon Vijay Abraham I33c1d772018-01-30 16:01:40 +01001626
1627#ifdef CONFIG_IODELAY_RECALIBRATION
1628static struct pad_conf_entry *
1629omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1630{
1631 int index = 0;
1632 struct pad_conf_entry *padconf;
1633
1634 padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1635 if (!padconf) {
1636 debug("failed to allocate memory\n");
1637 return 0;
1638 }
1639
1640 while (index < count) {
1641 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1642 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1643 index++;
1644 }
1645
1646 return padconf;
1647}
1648
1649static struct iodelay_cfg_entry *
1650omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1651{
1652 int index = 0;
1653 struct iodelay_cfg_entry *iodelay;
1654
1655 iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1656 if (!iodelay) {
1657 debug("failed to allocate memory\n");
1658 return 0;
1659 }
1660
1661 while (index < count) {
1662 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1663 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1664 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1665 index++;
1666 }
1667
1668 return iodelay;
1669}
1670
1671static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32 phandle,
1672 const char *name, int *len)
1673{
1674 const void *fdt = gd->fdt_blob;
1675 int offset;
1676 const fdt32_t *pinctrl;
1677
1678 offset = fdt_node_offset_by_phandle(fdt, phandle);
1679 if (offset < 0) {
1680 debug("failed to get pinctrl node %s.\n",
1681 fdt_strerror(offset));
1682 return 0;
1683 }
1684
1685 pinctrl = fdt_getprop(fdt, offset, name, len);
1686 if (!pinctrl) {
1687 debug("failed to get property %s\n", name);
1688 return 0;
1689 }
1690
1691 return pinctrl;
1692}
1693
1694static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1695 char *prop_name)
1696{
1697 const void *fdt = gd->fdt_blob;
1698 const __be32 *phandle;
1699 int node = dev_of_offset(mmc->dev);
1700
1701 phandle = fdt_getprop(fdt, node, prop_name, NULL);
1702 if (!phandle) {
1703 debug("failed to get property %s\n", prop_name);
1704 return 0;
1705 }
1706
1707 return fdt32_to_cpu(*phandle);
1708}
1709
1710static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1711 char *prop_name)
1712{
1713 const void *fdt = gd->fdt_blob;
1714 const __be32 *phandle;
1715 int len;
1716 int count;
1717 int node = dev_of_offset(mmc->dev);
1718
1719 phandle = fdt_getprop(fdt, node, prop_name, &len);
1720 if (!phandle) {
1721 debug("failed to get property %s\n", prop_name);
1722 return 0;
1723 }
1724
1725 /* No manual mode iodelay values if count < 2 */
1726 count = len / sizeof(*phandle);
1727 if (count < 2)
1728 return 0;
1729
1730 return fdt32_to_cpu(*(phandle + 1));
1731}
1732
1733static struct pad_conf_entry *
1734omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1735{
1736 int len;
1737 int count;
1738 struct pad_conf_entry *padconf;
1739 u32 phandle;
1740 const fdt32_t *pinctrl;
1741
1742 phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1743 if (!phandle)
1744 return ERR_PTR(-EINVAL);
1745
1746 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1747 &len);
1748 if (!pinctrl)
1749 return ERR_PTR(-EINVAL);
1750
1751 count = (len / sizeof(*pinctrl)) / 2;
1752 padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1753 if (!padconf)
1754 return ERR_PTR(-EINVAL);
1755
1756 *npads = count;
1757
1758 return padconf;
1759}
1760
1761static struct iodelay_cfg_entry *
1762omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1763{
1764 int len;
1765 int count;
1766 struct iodelay_cfg_entry *iodelay;
1767 u32 phandle;
1768 const fdt32_t *pinctrl;
1769
1770 phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1771 /* Not all modes have manual mode iodelay values. So its not fatal */
1772 if (!phandle)
1773 return 0;
1774
1775 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1776 &len);
1777 if (!pinctrl)
1778 return ERR_PTR(-EINVAL);
1779
1780 count = (len / sizeof(*pinctrl)) / 3;
1781 iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1782 if (!iodelay)
1783 return ERR_PTR(-EINVAL);
1784
1785 *niodelay = count;
1786
1787 return iodelay;
1788}
1789
1790static struct omap_hsmmc_pinctrl_state *
1791omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1792{
1793 int index;
1794 int npads = 0;
1795 int niodelays = 0;
1796 const void *fdt = gd->fdt_blob;
1797 int node = dev_of_offset(mmc->dev);
1798 char prop_name[11];
1799 struct omap_hsmmc_pinctrl_state *pinctrl_state;
1800
1801 pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1802 malloc(sizeof(*pinctrl_state));
1803 if (!pinctrl_state) {
1804 debug("failed to allocate memory\n");
1805 return 0;
1806 }
1807
1808 index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1809 if (index < 0) {
1810 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1811 goto err_pinctrl_state;
1812 }
1813
1814 sprintf(prop_name, "pinctrl-%d", index);
1815
1816 pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1817 &npads);
1818 if (IS_ERR(pinctrl_state->padconf))
1819 goto err_pinctrl_state;
1820 pinctrl_state->npads = npads;
1821
1822 pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1823 &niodelays);
1824 if (IS_ERR(pinctrl_state->iodelay))
1825 goto err_padconf;
1826 pinctrl_state->niodelays = niodelays;
1827
1828 return pinctrl_state;
1829
1830err_padconf:
1831 kfree(pinctrl_state->padconf);
1832
1833err_pinctrl_state:
1834 kfree(pinctrl_state);
1835 return 0;
1836}
1837
Jean-Jacques Hiblotbcc6bd82018-01-30 16:01:42 +01001838#define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional) \
Kishon Vijay Abraham I2d28eed2018-01-30 16:01:41 +01001839 do { \
1840 struct omap_hsmmc_pinctrl_state *s = NULL; \
1841 char str[20]; \
1842 if (!(cfg->host_caps & capmask)) \
1843 break; \
1844 \
1845 if (priv->hw_rev) { \
1846 sprintf(str, "%s-%s", #mode, priv->hw_rev); \
1847 s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \
1848 } \
1849 \
1850 if (!s) \
1851 s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1852 \
Jean-Jacques Hiblotbcc6bd82018-01-30 16:01:42 +01001853 if (!s && !optional) { \
Kishon Vijay Abraham I2d28eed2018-01-30 16:01:41 +01001854 debug("%s: no pinctrl for %s\n", \
1855 mmc->dev->name, #mode); \
1856 cfg->host_caps &= ~(capmask); \
1857 } else { \
1858 priv->mode##_pinctrl_state = s; \
1859 } \
Kishon Vijay Abraham I33c1d772018-01-30 16:01:40 +01001860 } while (0)
1861
1862static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1863{
1864 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1865 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1866 struct omap_hsmmc_pinctrl_state *default_pinctrl;
1867
1868 if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1869 return 0;
1870
1871 default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1872 if (!default_pinctrl) {
1873 printf("no pinctrl state for default mode\n");
1874 return -EINVAL;
1875 }
1876
1877 priv->default_pinctrl_state = default_pinctrl;
1878
Jean-Jacques Hiblotbcc6bd82018-01-30 16:01:42 +01001879 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1880 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1881 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1882 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1883 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
Kishon Vijay Abraham I33c1d772018-01-30 16:01:40 +01001884
Jean-Jacques Hiblotbcc6bd82018-01-30 16:01:42 +01001885 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1886 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1887 OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
Kishon Vijay Abraham I33c1d772018-01-30 16:01:40 +01001888
1889 return 0;
1890}
1891#endif
1892
Lokesh Vutla2558c042017-04-26 13:37:05 +05301893#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
Kishon Vijay Abraham I2d28eed2018-01-30 16:01:41 +01001894#ifdef CONFIG_OMAP54XX
1895__weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1896{
1897 return NULL;
1898}
1899#endif
1900
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301901static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1902{
Jean-Jacques Hiblot3d673ff2017-03-22 16:00:33 +01001903 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
Kishon Vijay Abraham I33c1d772018-01-30 16:01:40 +01001904 struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1905
Jean-Jacques Hiblot3d673ff2017-03-22 16:00:33 +01001906 struct mmc_config *cfg = &plat->cfg;
Kishon Vijay Abraham I2d28eed2018-01-30 16:01:41 +01001907#ifdef CONFIG_OMAP54XX
1908 const struct mmc_platform_fixups *fixups;
1909#endif
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301910 const void *fdt = gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -07001911 int node = dev_of_offset(dev);
Kishon Vijay Abraham I2d7482c2018-01-30 16:01:38 +01001912 int ret;
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301913
Simon Glassa821c4a2017-05-17 17:18:05 -06001914 plat->base_addr = map_physmem(devfdt_get_addr(dev),
1915 sizeof(struct hsmmc *),
Jean-Jacques Hiblot741726a2017-09-21 16:51:32 +02001916 MAP_NOCACHE);
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301917
Kishon Vijay Abraham I2d7482c2018-01-30 16:01:38 +01001918 ret = mmc_of_parse(dev, cfg);
1919 if (ret < 0)
1920 return ret;
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301921
Jean-Jacques Hiblotbeac7d32018-02-23 10:40:19 +01001922 if (!cfg->f_max)
1923 cfg->f_max = 52000000;
Kishon Vijay Abraham I2d7482c2018-01-30 16:01:38 +01001924 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301925 cfg->f_min = 400000;
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301926 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1927 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
Kishon Vijay Abraham Ib5944812018-01-30 16:01:32 +01001928 if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1929 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1930 if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1931 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
Kishon Vijay Abraham I33c1d772018-01-30 16:01:40 +01001932 if (of_data)
1933 plat->controller_flags |= of_data->controller_flags;
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301934
Kishon Vijay Abraham I2d28eed2018-01-30 16:01:41 +01001935#ifdef CONFIG_OMAP54XX
1936 fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1937 if (fixups) {
1938 plat->hw_rev = fixups->hw_rev;
1939 cfg->host_caps &= ~fixups->unsupported_caps;
1940 cfg->f_max = fixups->max_freq;
1941 }
1942#endif
1943
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301944 return 0;
1945}
Lokesh Vutla2558c042017-04-26 13:37:05 +05301946#endif
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301947
Jean-Jacques Hiblot17c9a1c2017-03-22 16:00:34 +01001948#ifdef CONFIG_BLK
1949
1950static int omap_hsmmc_bind(struct udevice *dev)
1951{
1952 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
Jean-Jacques Hiblot45530e32018-02-23 10:40:16 +01001953 plat->mmc = calloc(1, sizeof(struct mmc));
1954 return mmc_bind(dev, plat->mmc, &plat->cfg);
Jean-Jacques Hiblot17c9a1c2017-03-22 16:00:34 +01001955}
1956#endif
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301957static int omap_hsmmc_probe(struct udevice *dev)
1958{
Jean-Jacques Hiblot3d673ff2017-03-22 16:00:33 +01001959 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301960 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1961 struct omap_hsmmc_data *priv = dev_get_priv(dev);
Jean-Jacques Hiblot3d673ff2017-03-22 16:00:33 +01001962 struct mmc_config *cfg = &plat->cfg;
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301963 struct mmc *mmc;
Kishon Vijay Abraham I33c1d772018-01-30 16:01:40 +01001964#ifdef CONFIG_IODELAY_RECALIBRATION
1965 int ret;
1966#endif
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301967
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301968 cfg->name = "OMAP SD/MMC";
Lokesh Vutla2558c042017-04-26 13:37:05 +05301969 priv->base_addr = plat->base_addr;
Kishon Vijay Abraham I33c1d772018-01-30 16:01:40 +01001970 priv->controller_flags = plat->controller_flags;
Kishon Vijay Abraham I2d28eed2018-01-30 16:01:41 +01001971 priv->hw_rev = plat->hw_rev;
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301972
Jean-Jacques Hiblot17c9a1c2017-03-22 16:00:34 +01001973#ifdef CONFIG_BLK
Jean-Jacques Hiblot45530e32018-02-23 10:40:16 +01001974 mmc = plat->mmc;
Jean-Jacques Hiblot17c9a1c2017-03-22 16:00:34 +01001975#else
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301976 mmc = mmc_create(cfg, priv);
1977 if (mmc == NULL)
1978 return -1;
Jean-Jacques Hiblot17c9a1c2017-03-22 16:00:34 +01001979#endif
Jean-Jacques Hiblot04f9f8b2018-01-30 16:01:46 +01001980#if CONFIG_IS_ENABLED(DM_REGULATOR)
1981 device_get_supply_regulator(dev, "pbias-supply",
1982 &priv->pbias_supply);
1983#endif
Adam Ford307a2142018-08-21 07:16:56 -05001984#if defined(OMAP_HSMMC_USE_GPIO)
1985#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
Mugunthan V N5cc6a242016-04-04 17:28:01 +05301986 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1987 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1988#endif
Adam Ford307a2142018-08-21 07:16:56 -05001989#endif
Mugunthan V N5cc6a242016-04-04 17:28:01 +05301990
Simon Glasscffe5d82016-05-01 13:52:34 -06001991 mmc->dev = dev;
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05301992 upriv->mmc = mmc;
1993
Kishon Vijay Abraham I33c1d772018-01-30 16:01:40 +01001994#ifdef CONFIG_IODELAY_RECALIBRATION
1995 ret = omap_hsmmc_get_pinctrl_state(mmc);
1996 /*
1997 * disable high speed modes for the platforms that require IO delay
1998 * and for which we don't have this information
1999 */
2000 if ((ret < 0) &&
2001 (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
2002 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
2003 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
2004 UHS_CAPS);
2005 }
2006#endif
2007
Jean-Jacques Hiblotb5511d62017-04-14 19:50:02 +02002008 return omap_hsmmc_init_setup(mmc);
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05302009}
2010
Lokesh Vutla2558c042017-04-26 13:37:05 +05302011#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
Kishon Vijay Abraham I33c1d772018-01-30 16:01:40 +01002012
2013static const struct omap_mmc_of_data dra7_mmc_of_data = {
2014 .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
2015};
2016
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05302017static const struct udevice_id omap_hsmmc_ids[] = {
Jean-Jacques Hiblot741726a2017-09-21 16:51:32 +02002018 { .compatible = "ti,omap3-hsmmc" },
2019 { .compatible = "ti,omap4-hsmmc" },
2020 { .compatible = "ti,am33xx-hsmmc" },
Kishon Vijay Abraham I33c1d772018-01-30 16:01:40 +01002021 { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05302022 { }
2023};
Lokesh Vutla2558c042017-04-26 13:37:05 +05302024#endif
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05302025
2026U_BOOT_DRIVER(omap_hsmmc) = {
2027 .name = "omap_hsmmc",
2028 .id = UCLASS_MMC,
Lokesh Vutla2558c042017-04-26 13:37:05 +05302029#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05302030 .of_match = omap_hsmmc_ids,
2031 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
Lokesh Vutla2558c042017-04-26 13:37:05 +05302032 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
2033#endif
Jean-Jacques Hiblot17c9a1c2017-03-22 16:00:34 +01002034#ifdef CONFIG_BLK
2035 .bind = omap_hsmmc_bind,
2036#endif
Jean-Jacques Hiblotb5511d62017-04-14 19:50:02 +02002037 .ops = &omap_hsmmc_ops,
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05302038 .probe = omap_hsmmc_probe,
2039 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
Bin Meng223b10c2018-10-24 06:36:32 -07002040#if !CONFIG_IS_ENABLED(OF_CONTROL)
Lokesh Vutlacbcb1702017-04-26 13:37:06 +05302041 .flags = DM_FLAG_PRE_RELOC,
Bin Meng223b10c2018-10-24 06:36:32 -07002042#endif
Mugunthan V Na9d6a7e2015-09-28 12:56:30 +05302043};
2044#endif