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Wolfgang Wegner9d79e572010-01-25 11:27:44 +01001/*
2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Wegner9d79e572010-01-25 11:27:44 +01007 */
8
9#include <common.h>
10#include <watchdog.h>
11#include <command.h>
12#include <asm/m5329.h>
13#include <asm/immap_5329.h>
14#include <asm/io.h>
15
16/* needed for astro bus: */
17#include <asm/uart.h>
18#include "astro.h"
19
20DECLARE_GLOBAL_DATA_PTR;
21extern void uart_port_conf(void);
22
23int checkboard(void)
24{
25 puts("Board: ");
26 puts("ASTRO MCF5373L (Urmel) Board\n");
27 return 0;
28}
29
30phys_size_t initdram(int board_type)
31{
32#if !defined(CONFIG_MONITOR_IS_IN_RAM)
33 sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
34
35 /*
36 * GPIO configuration for bus should be set correctly from reset,
37 * so we do not care! First, set up address space: at this point,
38 * we should be running from internal SRAM;
39 * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM,
40 * and do not care where it is
41 */
42 __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
43 &sdp->cs0);
44 __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
45 &sdp->cs1);
46 /*
47 * I am not sure from the data sheet, but it seems burst length
48 * has to be 8 for the 16 bit data bus we use;
49 * so these values are for BL = 8
50 */
51 __raw_writel(0x33211530, &sdp->cfg1);
52 __raw_writel(0x56570000, &sdp->cfg2);
53 /* send PrechargeALL, REF and IREF remain cleared! */
54 __raw_writel(0xE1462C02, &sdp->ctrl);
55 udelay(1);
56 /* refresh SDRAM twice */
57 __raw_writel(0xE1462C04, &sdp->ctrl);
58 udelay(1);
59 __raw_writel(0xE1462C04, &sdp->ctrl);
60 /* init MR */
61 __raw_writel(0x008D0000, &sdp->mode);
62 /* initialize EMR */
63 __raw_writel(0x80010000, &sdp->mode);
64 /* wait until DLL is locked */
65 udelay(1);
66 /*
67 * enable automatic refresh, lock mode register,
68 * clear iref and ipall
69 */
70 __raw_writel(0x71462C00, &sdp->ctrl);
71 /* Dummy write to start SDRAM */
72 writel(0, CONFIG_SYS_SDRAM_BASE);
73#endif
74
75 /*
76 * for get_ram_size() to work, both CS areas have to be
77 * configured, i.e. CS1 has to be explicitely disabled, else
78 * probing for memory will cause the SDRAM bus to hang!
79 * (Do not rely on the SDCS register(s) being set to 0x00000000
80 * during reset as stated in the data sheet.)
81 */
82 return get_ram_size((unsigned long *)CONFIG_SYS_SDRAM_BASE,
83 0x80000000 - CONFIG_SYS_SDRAM_BASE);
84}
85
86#define UART_BASE MMAP_UART0
87int rs_serial_init(int port, int baud)
88{
89 uart_t *uart;
90 u32 counter;
91
92 switch (port) {
93 case 0:
94 uart = (uart_t *)(MMAP_UART0);
95 break;
96 case 1:
97 uart = (uart_t *)(MMAP_UART1);
98 break;
99 case 2:
100 uart = (uart_t *)(MMAP_UART2);
101 break;
102 default:
103 uart = (uart_t *)(MMAP_UART0);
104 }
105
106 uart_port_conf();
107
108 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */
109 writeb(UART_UCR_RESET_RX, &uart->ucr);
110 writeb(UART_UCR_RESET_TX, &uart->ucr);
111 writeb(UART_UCR_RESET_ERROR, &uart->ucr);
112 writeb(UART_UCR_RESET_MR, &uart->ucr);
113 __asm__ ("nop");
114
115 writeb(0, &uart->uimr);
116
117 /* write to CSR: RX/TX baud rate from timers */
118 writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
119
120 writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
121 writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
122
123 /* Setting up BaudRate */
124 counter = (u32) (gd->bus_clk / (baud));
125 counter >>= 5;
126
127 /* write to CTUR: divide counter upper byte */
128 writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1);
129 /* write to CTLR: divide counter lower byte */
130 writeb((u8) (counter & 0x00ff), &uart->ubg2);
131
132 writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
133
134 return 0;
135}
136
137void astro_put_char(char ch)
138{
139 uart_t *uart;
140 unsigned long timer;
141
142 uart = (uart_t *)(MMAP_UART0);
143 /*
144 * Wait for last character to go. Timeout of 6ms should
145 * be enough for our lowest baud rate of 2400.
146 */
147 timer = get_timer(0);
148 while (get_timer(timer) < 6) {
149 if (readb(&uart->usr) & UART_USR_TXRDY)
150 break;
151 }
152 writeb(ch, &uart->utb);
153
154 return;
155}
156
157int astro_is_char(void)
158{
159 uart_t *uart;
160
161 uart = (uart_t *)(MMAP_UART0);
162 return readb(&uart->usr) & UART_USR_RXRDY;
163}
164
165int astro_get_char(void)
166{
167 uart_t *uart;
168
169 uart = (uart_t *)(MMAP_UART0);
170 while (!(readb(&uart->usr) & UART_USR_RXRDY)) ;
171 return readb(&uart->urb);
172}
173
174int misc_init_r(void)
175{
176 int retval = 0;
177
178 puts("Configure Xilinx FPGA...");
179 retval = astro5373l_xilinx_load();
180 if (!retval) {
181 puts("failed!\n");
182 return retval;
183 }
184 puts("done\n");
185
186 puts("Configure Altera FPGA...");
187 retval = astro5373l_altera_load();
188 if (!retval) {
189 puts("failed!\n");
190 return retval;
191 }
192 puts("done\n");
193
194 return retval;
195}