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Kumar Gala58e5e9a2008-08-26 15:01:29 -05001/*
York Sun34e026f2014-03-27 17:54:47 -07002 * Copyright 2008-2014 Freescale Semiconductor, Inc.
Kumar Gala58e5e9a2008-08-26 15:01:29 -05003 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9#ifndef FSL_DDR_MAIN_H
10#define FSL_DDR_MAIN_H
11
York Sun34e026f2014-03-27 17:54:47 -070012#include <fsl_ddrc_version.h>
York Sun5614e712013-09-30 09:22:09 -070013#include <fsl_ddr_sdram.h>
14#include <fsl_ddr_dimm_params.h>
Kumar Gala58e5e9a2008-08-26 15:01:29 -050015
York Sun5614e712013-09-30 09:22:09 -070016#include <common_timing_params.h>
Kumar Gala58e5e9a2008-08-26 15:01:29 -050017
York Sun1d71efb2014-08-01 15:51:00 -070018#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
19/* All controllers are for main memory */
20#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_NUM_DDR_CONTROLLERS
21#endif
22
York Sun4e5b1bd2014-02-10 13:59:42 -080023#ifdef CONFIG_SYS_FSL_DDR_LE
24#define ddr_in32(a) in_le32(a)
25#define ddr_out32(a, v) out_le32(a, v)
York Sundda3b612014-12-08 15:30:55 -080026#define ddr_setbits32(a, v) setbits_le32(a, v)
27#define ddr_clrbits32(a, v) clrbits_le32(a, v)
28#define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set)
York Sun4e5b1bd2014-02-10 13:59:42 -080029#else
30#define ddr_in32(a) in_be32(a)
31#define ddr_out32(a, v) out_be32(a, v)
York Sundda3b612014-12-08 15:30:55 -080032#define ddr_setbits32(a, v) setbits_be32(a, v)
33#define ddr_clrbits32(a, v) clrbits_be32(a, v)
34#define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
York Sun4e5b1bd2014-02-10 13:59:42 -080035#endif
36
York Sun34e026f2014-03-27 17:54:47 -070037#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
38
39u32 fsl_ddr_get_version(void);
40
York Sun1b3e3c42011-06-07 09:42:16 +080041#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
Kumar Gala58e5e9a2008-08-26 15:01:29 -050042/*
43 * Bind the main DDR setup driver's generic names
44 * to this specific DDR technology.
45 */
46static __inline__ int
47compute_dimm_parameters(const generic_spd_eeprom_t *spd,
48 dimm_params_t *pdimm,
49 unsigned int dimm_number)
50{
51 return ddr_compute_dimm_parameters(spd, pdimm, dimm_number);
52}
York Sun1b3e3c42011-06-07 09:42:16 +080053#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -050054
55/*
56 * Data Structures
57 *
58 * All data structures have to be on the stack
59 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS
61#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
Kumar Gala58e5e9a2008-08-26 15:01:29 -050062
63typedef struct {
64 generic_spd_eeprom_t
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065 spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
Kumar Gala58e5e9a2008-08-26 15:01:29 -050066 struct dimm_params_s
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067 dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
68 memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
69 common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
70 fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
York Sun1d71efb2014-08-01 15:51:00 -070071 unsigned int first_ctrl;
72 unsigned int num_ctrls;
73 unsigned long long mem_base;
74 unsigned int dimm_slots_per_ctrl;
75 int (*board_need_mem_reset)(void);
76 void (*board_mem_reset)(void);
77 void (*board_mem_de_reset)(void);
Kumar Gala58e5e9a2008-08-26 15:01:29 -050078} fsl_ddr_info_t;
79
80/* Compute steps */
81#define STEP_GET_SPD (1 << 0)
82#define STEP_COMPUTE_DIMM_PARMS (1 << 1)
83#define STEP_COMPUTE_COMMON_PARMS (1 << 2)
84#define STEP_GATHER_OPTS (1 << 3)
85#define STEP_ASSIGN_ADDRESSES (1 << 4)
86#define STEP_COMPUTE_REGS (1 << 5)
87#define STEP_PROGRAM_REGS (1 << 6)
88#define STEP_ALL 0xFFF
89
York Sun6f5e1dc2011-09-16 13:21:35 -070090unsigned long long
Haiying Wangfc0c2b62010-12-01 10:35:31 -050091fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
92 unsigned int size_only);
York Sun6f5e1dc2011-09-16 13:21:35 -070093const char *step_to_string(unsigned int step);
Kumar Gala58e5e9a2008-08-26 15:01:29 -050094
York Sun6f5e1dc2011-09-16 13:21:35 -070095unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts,
Kumar Gala58e5e9a2008-08-26 15:01:29 -050096 fsl_ddr_cfg_regs_t *ddr,
97 const common_timing_params_t *common_dimm,
98 const dimm_params_t *dimm_parameters,
Haiying Wangfc0c2b62010-12-01 10:35:31 -050099 unsigned int dbw_capacity_adjust,
100 unsigned int size_only);
York Sun6f5e1dc2011-09-16 13:21:35 -0700101unsigned int compute_lowest_common_dimm_parameters(
102 const dimm_params_t *dimm_params,
103 common_timing_params_t *outpdimm,
104 unsigned int number_of_dimms);
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530105unsigned int populate_memctl_options(int all_dimms_registered,
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500106 memctl_options_t *popts,
Haiying Wangdfb49102008-10-03 12:36:55 -0400107 dimm_params_t *pdimm,
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500108 unsigned int ctrl_num);
York Sun6f5e1dc2011-09-16 13:21:35 -0700109void check_interleaving_options(fsl_ddr_info_t *pinfo);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500110
York Sun6f5e1dc2011-09-16 13:21:35 -0700111unsigned int mclk_to_picos(unsigned int mclk);
112unsigned int get_memory_clk_period_ps(void);
113unsigned int picos_to_mclk(unsigned int picos);
114void fsl_ddr_set_lawbar(
115 const common_timing_params_t *memctl_common_params,
116 unsigned int memctl_interleaved,
117 unsigned int ctrl_num);
118
James Yange8ba6c52013-01-07 14:01:03 +0000119int fsl_ddr_interactive_env_var_exists(void);
120unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
York Sun6f5e1dc2011-09-16 13:21:35 -0700121void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
York Sun1d71efb2014-08-01 15:51:00 -0700122 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
York Sun6f5e1dc2011-09-16 13:21:35 -0700123
124int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
125unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
York Sun4e5b1bd2014-02-10 13:59:42 -0800126void board_add_ram_info(int use_default);
York Sun6f5e1dc2011-09-16 13:21:35 -0700127
128/* processor specific function */
129void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
York Sunc63e1372013-06-25 11:37:48 -0700130 unsigned int ctrl_num, int step);
York Sun1b3e3c42011-06-07 09:42:16 +0800131
132/* board specific function */
133int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
134 unsigned int controller_number,
135 unsigned int dimm_number);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500136#endif