| Mike Frysinger | d4d7730 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 1 | /* DO NOT EDIT THIS FILE |
| 2 | * Automatically generated by generate-cdef-headers.xsl |
| 3 | * DO NOT EDIT THIS FILE |
| 4 | */ |
| 5 | |
| 6 | #ifndef __BFIN_CDEF_ADSP_EDN_extended__ |
| 7 | #define __BFIN_CDEF_ADSP_EDN_extended__ |
| 8 | |
| 9 | #define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ |
| 10 | #define bfin_read_ILAT() bfin_read32(ILAT) |
| 11 | #define bfin_write_ILAT(val) bfin_write32(ILAT, val) |
| 12 | #define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ |
| 13 | #define bfin_read_IMASK() bfin_read32(IMASK) |
| 14 | #define bfin_write_IMASK(val) bfin_write32(IMASK, val) |
| 15 | #define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ |
| 16 | #define bfin_read_IPEND() bfin_read32(IPEND) |
| 17 | #define bfin_write_IPEND(val) bfin_write32(IPEND, val) |
| 18 | #define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ |
| 19 | #define bfin_read_IPRIO() bfin_read32(IPRIO) |
| 20 | #define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) |
| 21 | #define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ |
| 22 | #define bfin_read_TCNTL() bfin_read32(TCNTL) |
| 23 | #define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) |
| 24 | #define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ |
| 25 | #define bfin_read_TPERIOD() bfin_read32(TPERIOD) |
| 26 | #define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) |
| 27 | #define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ |
| 28 | #define bfin_read_TSCALE() bfin_read32(TSCALE) |
| 29 | #define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) |
| 30 | #define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ |
| 31 | #define bfin_read_TCOUNT() bfin_read32(TCOUNT) |
| 32 | #define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) |
| 33 | #define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ |
| 34 | #define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) |
| 35 | #define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) |
| 36 | #define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ |
| 37 | #define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) |
| 38 | #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) |
| 39 | #define pDCPLB_FAULT_STATUS ((uint32_t volatile *)DCPLB_FAULT_STATUS) /* L1 Data Memory Controller Register */ |
| 40 | #define bfin_read_DCPLB_FAULT_STATUS() bfin_read32(DCPLB_FAULT_STATUS) |
| 41 | #define bfin_write_DCPLB_FAULT_STATUS(val) bfin_write32(DCPLB_FAULT_STATUS, val) |
| 42 | #define pDCPLB_FAULT_ADDR ((uint32_t volatile *)DCPLB_FAULT_ADDR) |
| 43 | #define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR) |
| 44 | #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR, val) |
| 45 | #define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ |
| 46 | #define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) |
| 47 | #define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) |
| 48 | #define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ |
| 49 | #define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) |
| 50 | #define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) |
| 51 | #define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ |
| 52 | #define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) |
| 53 | #define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) |
| 54 | #define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ |
| 55 | #define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) |
| 56 | #define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) |
| 57 | #define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ |
| 58 | #define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) |
| 59 | #define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) |
| 60 | #define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ |
| 61 | #define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) |
| 62 | #define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) |
| 63 | #define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ |
| 64 | #define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) |
| 65 | #define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) |
| 66 | #define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ |
| 67 | #define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) |
| 68 | #define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) |
| 69 | #define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ |
| 70 | #define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) |
| 71 | #define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) |
| 72 | #define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ |
| 73 | #define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) |
| 74 | #define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) |
| 75 | #define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ |
| 76 | #define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) |
| 77 | #define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) |
| 78 | #define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ |
| 79 | #define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) |
| 80 | #define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) |
| 81 | #define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ |
| 82 | #define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) |
| 83 | #define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) |
| 84 | #define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ |
| 85 | #define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) |
| 86 | #define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) |
| 87 | #define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ |
| 88 | #define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) |
| 89 | #define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) |
| 90 | #define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ |
| 91 | #define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) |
| 92 | #define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) |
| 93 | #define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ |
| 94 | #define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) |
| 95 | #define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) |
| 96 | #define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ |
| 97 | #define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) |
| 98 | #define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) |
| 99 | #define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ |
| 100 | #define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) |
| 101 | #define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) |
| 102 | #define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ |
| 103 | #define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) |
| 104 | #define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) |
| 105 | #define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ |
| 106 | #define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) |
| 107 | #define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) |
| 108 | #define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ |
| 109 | #define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) |
| 110 | #define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) |
| 111 | #define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ |
| 112 | #define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) |
| 113 | #define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) |
| 114 | #define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ |
| 115 | #define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) |
| 116 | #define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) |
| 117 | #define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ |
| 118 | #define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) |
| 119 | #define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) |
| 120 | #define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ |
| 121 | #define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) |
| 122 | #define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) |
| 123 | #define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ |
| 124 | #define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) |
| 125 | #define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) |
| 126 | #define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ |
| 127 | #define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) |
| 128 | #define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) |
| 129 | #define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ |
| 130 | #define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) |
| 131 | #define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) |
| 132 | #define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ |
| 133 | #define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) |
| 134 | #define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) |
| 135 | #define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ |
| 136 | #define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) |
| 137 | #define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) |
| 138 | #define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ |
| 139 | #define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) |
| 140 | #define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) |
| 141 | #define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ |
| 142 | #define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) |
| 143 | #define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) |
| 144 | #define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ |
| 145 | #define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) |
| 146 | #define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) |
| 147 | #define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ |
| 148 | #define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) |
| 149 | #define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) |
| 150 | #define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ |
| 151 | #define bfin_read_EVT0() bfin_readPTR(EVT0) |
| 152 | #define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) |
| 153 | #define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ |
| 154 | #define bfin_read_EVT1() bfin_readPTR(EVT1) |
| 155 | #define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) |
| 156 | #define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ |
| 157 | #define bfin_read_EVT2() bfin_readPTR(EVT2) |
| 158 | #define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) |
| 159 | #define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ |
| 160 | #define bfin_read_EVT3() bfin_readPTR(EVT3) |
| 161 | #define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) |
| 162 | #define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ |
| 163 | #define bfin_read_EVT4() bfin_readPTR(EVT4) |
| 164 | #define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) |
| 165 | #define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ |
| 166 | #define bfin_read_EVT5() bfin_readPTR(EVT5) |
| 167 | #define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) |
| 168 | #define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ |
| 169 | #define bfin_read_EVT6() bfin_readPTR(EVT6) |
| 170 | #define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) |
| 171 | #define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ |
| 172 | #define bfin_read_EVT7() bfin_readPTR(EVT7) |
| 173 | #define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) |
| 174 | #define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ |
| 175 | #define bfin_read_EVT8() bfin_readPTR(EVT8) |
| 176 | #define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) |
| 177 | #define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ |
| 178 | #define bfin_read_EVT9() bfin_readPTR(EVT9) |
| 179 | #define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) |
| 180 | #define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ |
| 181 | #define bfin_read_EVT10() bfin_readPTR(EVT10) |
| 182 | #define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) |
| 183 | #define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ |
| 184 | #define bfin_read_EVT11() bfin_readPTR(EVT11) |
| 185 | #define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) |
| 186 | #define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ |
| 187 | #define bfin_read_EVT12() bfin_readPTR(EVT12) |
| 188 | #define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) |
| 189 | #define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ |
| 190 | #define bfin_read_EVT13() bfin_readPTR(EVT13) |
| 191 | #define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) |
| 192 | #define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ |
| 193 | #define bfin_read_EVT14() bfin_readPTR(EVT14) |
| 194 | #define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) |
| 195 | #define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ |
| 196 | #define bfin_read_EVT15() bfin_readPTR(EVT15) |
| 197 | #define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) |
| 198 | #define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ |
| 199 | #define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) |
| 200 | #define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) |
| 201 | #define pICPLB_FAULT_STATUS ((uint32_t volatile *)ICPLB_FAULT_STATUS) |
| 202 | #define bfin_read_ICPLB_FAULT_STATUS() bfin_read32(ICPLB_FAULT_STATUS) |
| 203 | #define bfin_write_ICPLB_FAULT_STATUS(val) bfin_write32(ICPLB_FAULT_STATUS, val) |
| 204 | #define pICPLB_FAULT_ADDR ((uint32_t volatile *)ICPLB_FAULT_ADDR) |
| 205 | #define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR) |
| 206 | #define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val) |
| 207 | #define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ |
| 208 | #define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) |
| 209 | #define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) |
| 210 | #define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ |
| 211 | #define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) |
| 212 | #define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) |
| 213 | #define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ |
| 214 | #define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) |
| 215 | #define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) |
| 216 | #define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ |
| 217 | #define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) |
| 218 | #define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) |
| 219 | #define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ |
| 220 | #define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) |
| 221 | #define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) |
| 222 | #define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ |
| 223 | #define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) |
| 224 | #define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) |
| 225 | #define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ |
| 226 | #define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) |
| 227 | #define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) |
| 228 | #define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ |
| 229 | #define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) |
| 230 | #define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) |
| 231 | #define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ |
| 232 | #define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) |
| 233 | #define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) |
| 234 | #define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ |
| 235 | #define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) |
| 236 | #define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) |
| 237 | #define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ |
| 238 | #define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) |
| 239 | #define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) |
| 240 | #define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ |
| 241 | #define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) |
| 242 | #define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) |
| 243 | #define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ |
| 244 | #define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) |
| 245 | #define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) |
| 246 | #define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ |
| 247 | #define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) |
| 248 | #define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) |
| 249 | #define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ |
| 250 | #define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) |
| 251 | #define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) |
| 252 | #define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ |
| 253 | #define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) |
| 254 | #define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) |
| 255 | #define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ |
| 256 | #define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) |
| 257 | #define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) |
| 258 | #define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ |
| 259 | #define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) |
| 260 | #define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) |
| 261 | #define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ |
| 262 | #define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) |
| 263 | #define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) |
| 264 | #define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ |
| 265 | #define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) |
| 266 | #define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) |
| 267 | #define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ |
| 268 | #define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) |
| 269 | #define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) |
| 270 | #define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ |
| 271 | #define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) |
| 272 | #define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) |
| 273 | #define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ |
| 274 | #define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) |
| 275 | #define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) |
| 276 | #define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ |
| 277 | #define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) |
| 278 | #define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) |
| 279 | #define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ |
| 280 | #define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) |
| 281 | #define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) |
| 282 | #define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ |
| 283 | #define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) |
| 284 | #define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) |
| 285 | #define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ |
| 286 | #define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) |
| 287 | #define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) |
| 288 | #define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ |
| 289 | #define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) |
| 290 | #define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) |
| 291 | #define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ |
| 292 | #define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) |
| 293 | #define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) |
| 294 | #define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ |
| 295 | #define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) |
| 296 | #define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) |
| 297 | #define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ |
| 298 | #define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) |
| 299 | #define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) |
| 300 | #define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ |
| 301 | #define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) |
| 302 | #define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) |
| 303 | #define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ |
| 304 | #define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) |
| 305 | #define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) |
| 306 | #define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ |
| 307 | #define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) |
| 308 | #define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) |
| 309 | #define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ |
| 310 | #define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) |
| 311 | #define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) |
| 312 | #define pMDMAFLX0_DMACNFG_D ((uint16_t volatile *)MDMAFLX0_DMACNFG_D) |
| 313 | #define bfin_read_MDMAFLX0_DMACNFG_D() bfin_read16(MDMAFLX0_DMACNFG_D) |
| 314 | #define bfin_write_MDMAFLX0_DMACNFG_D(val) bfin_write16(MDMAFLX0_DMACNFG_D, val) |
| 315 | #define pMDMAFLX0_XCOUNT_D ((uint16_t volatile *)MDMAFLX0_XCOUNT_D) |
| 316 | #define bfin_read_MDMAFLX0_XCOUNT_D() bfin_read16(MDMAFLX0_XCOUNT_D) |
| 317 | #define bfin_write_MDMAFLX0_XCOUNT_D(val) bfin_write16(MDMAFLX0_XCOUNT_D, val) |
| 318 | #define pMDMAFLX0_XMODIFY_D ((uint16_t volatile *)MDMAFLX0_XMODIFY_D) |
| 319 | #define bfin_read_MDMAFLX0_XMODIFY_D() bfin_read16(MDMAFLX0_XMODIFY_D) |
| 320 | #define bfin_write_MDMAFLX0_XMODIFY_D(val) bfin_write16(MDMAFLX0_XMODIFY_D, val) |
| 321 | #define pMDMAFLX0_YCOUNT_D ((uint16_t volatile *)MDMAFLX0_YCOUNT_D) |
| 322 | #define bfin_read_MDMAFLX0_YCOUNT_D() bfin_read16(MDMAFLX0_YCOUNT_D) |
| 323 | #define bfin_write_MDMAFLX0_YCOUNT_D(val) bfin_write16(MDMAFLX0_YCOUNT_D, val) |
| 324 | #define pMDMAFLX0_YMODIFY_D ((uint16_t volatile *)MDMAFLX0_YMODIFY_D) |
| 325 | #define bfin_read_MDMAFLX0_YMODIFY_D() bfin_read16(MDMAFLX0_YMODIFY_D) |
| 326 | #define bfin_write_MDMAFLX0_YMODIFY_D(val) bfin_write16(MDMAFLX0_YMODIFY_D, val) |
| 327 | #define pMDMAFLX0_IRQSTAT_D ((uint16_t volatile *)MDMAFLX0_IRQSTAT_D) |
| 328 | #define bfin_read_MDMAFLX0_IRQSTAT_D() bfin_read16(MDMAFLX0_IRQSTAT_D) |
| 329 | #define bfin_write_MDMAFLX0_IRQSTAT_D(val) bfin_write16(MDMAFLX0_IRQSTAT_D, val) |
| 330 | #define pMDMAFLX0_PMAP_D ((uint16_t volatile *)MDMAFLX0_PMAP_D) |
| 331 | #define bfin_read_MDMAFLX0_PMAP_D() bfin_read16(MDMAFLX0_PMAP_D) |
| 332 | #define bfin_write_MDMAFLX0_PMAP_D(val) bfin_write16(MDMAFLX0_PMAP_D, val) |
| 333 | #define pMDMAFLX0_CURXCOUNT_D ((uint16_t volatile *)MDMAFLX0_CURXCOUNT_D) |
| 334 | #define bfin_read_MDMAFLX0_CURXCOUNT_D() bfin_read16(MDMAFLX0_CURXCOUNT_D) |
| 335 | #define bfin_write_MDMAFLX0_CURXCOUNT_D(val) bfin_write16(MDMAFLX0_CURXCOUNT_D, val) |
| 336 | #define pMDMAFLX0_CURYCOUNT_D ((uint16_t volatile *)MDMAFLX0_CURYCOUNT_D) |
| 337 | #define bfin_read_MDMAFLX0_CURYCOUNT_D() bfin_read16(MDMAFLX0_CURYCOUNT_D) |
| 338 | #define bfin_write_MDMAFLX0_CURYCOUNT_D(val) bfin_write16(MDMAFLX0_CURYCOUNT_D, val) |
| 339 | #define pMDMAFLX0_DMACNFG_S ((uint16_t volatile *)MDMAFLX0_DMACNFG_S) |
| 340 | #define bfin_read_MDMAFLX0_DMACNFG_S() bfin_read16(MDMAFLX0_DMACNFG_S) |
| 341 | #define bfin_write_MDMAFLX0_DMACNFG_S(val) bfin_write16(MDMAFLX0_DMACNFG_S, val) |
| 342 | #define pMDMAFLX0_XCOUNT_S ((uint16_t volatile *)MDMAFLX0_XCOUNT_S) |
| 343 | #define bfin_read_MDMAFLX0_XCOUNT_S() bfin_read16(MDMAFLX0_XCOUNT_S) |
| 344 | #define bfin_write_MDMAFLX0_XCOUNT_S(val) bfin_write16(MDMAFLX0_XCOUNT_S, val) |
| 345 | #define pMDMAFLX0_XMODIFY_S ((uint16_t volatile *)MDMAFLX0_XMODIFY_S) |
| 346 | #define bfin_read_MDMAFLX0_XMODIFY_S() bfin_read16(MDMAFLX0_XMODIFY_S) |
| 347 | #define bfin_write_MDMAFLX0_XMODIFY_S(val) bfin_write16(MDMAFLX0_XMODIFY_S, val) |
| 348 | #define pMDMAFLX0_YCOUNT_S ((uint16_t volatile *)MDMAFLX0_YCOUNT_S) |
| 349 | #define bfin_read_MDMAFLX0_YCOUNT_S() bfin_read16(MDMAFLX0_YCOUNT_S) |
| 350 | #define bfin_write_MDMAFLX0_YCOUNT_S(val) bfin_write16(MDMAFLX0_YCOUNT_S, val) |
| 351 | #define pMDMAFLX0_YMODIFY_S ((uint16_t volatile *)MDMAFLX0_YMODIFY_S) |
| 352 | #define bfin_read_MDMAFLX0_YMODIFY_S() bfin_read16(MDMAFLX0_YMODIFY_S) |
| 353 | #define bfin_write_MDMAFLX0_YMODIFY_S(val) bfin_write16(MDMAFLX0_YMODIFY_S, val) |
| 354 | #define pMDMAFLX0_IRQSTAT_S ((uint16_t volatile *)MDMAFLX0_IRQSTAT_S) |
| 355 | #define bfin_read_MDMAFLX0_IRQSTAT_S() bfin_read16(MDMAFLX0_IRQSTAT_S) |
| 356 | #define bfin_write_MDMAFLX0_IRQSTAT_S(val) bfin_write16(MDMAFLX0_IRQSTAT_S, val) |
| 357 | #define pMDMAFLX0_PMAP_S ((uint16_t volatile *)MDMAFLX0_PMAP_S) |
| 358 | #define bfin_read_MDMAFLX0_PMAP_S() bfin_read16(MDMAFLX0_PMAP_S) |
| 359 | #define bfin_write_MDMAFLX0_PMAP_S(val) bfin_write16(MDMAFLX0_PMAP_S, val) |
| 360 | #define pMDMAFLX0_CURXCOUNT_S ((uint16_t volatile *)MDMAFLX0_CURXCOUNT_S) |
| 361 | #define bfin_read_MDMAFLX0_CURXCOUNT_S() bfin_read16(MDMAFLX0_CURXCOUNT_S) |
| 362 | #define bfin_write_MDMAFLX0_CURXCOUNT_S(val) bfin_write16(MDMAFLX0_CURXCOUNT_S, val) |
| 363 | #define pMDMAFLX0_CURYCOUNT_S ((uint16_t volatile *)MDMAFLX0_CURYCOUNT_S) |
| 364 | #define bfin_read_MDMAFLX0_CURYCOUNT_S() bfin_read16(MDMAFLX0_CURYCOUNT_S) |
| 365 | #define bfin_write_MDMAFLX0_CURYCOUNT_S(val) bfin_write16(MDMAFLX0_CURYCOUNT_S, val) |
| 366 | #define pMDMAFLX1_DMACNFG_D ((uint16_t volatile *)MDMAFLX1_DMACNFG_D) |
| 367 | #define bfin_read_MDMAFLX1_DMACNFG_D() bfin_read16(MDMAFLX1_DMACNFG_D) |
| 368 | #define bfin_write_MDMAFLX1_DMACNFG_D(val) bfin_write16(MDMAFLX1_DMACNFG_D, val) |
| 369 | #define pMDMAFLX1_XCOUNT_D ((uint16_t volatile *)MDMAFLX1_XCOUNT_D) |
| 370 | #define bfin_read_MDMAFLX1_XCOUNT_D() bfin_read16(MDMAFLX1_XCOUNT_D) |
| 371 | #define bfin_write_MDMAFLX1_XCOUNT_D(val) bfin_write16(MDMAFLX1_XCOUNT_D, val) |
| 372 | #define pMDMAFLX1_XMODIFY_D ((uint16_t volatile *)MDMAFLX1_XMODIFY_D) |
| 373 | #define bfin_read_MDMAFLX1_XMODIFY_D() bfin_read16(MDMAFLX1_XMODIFY_D) |
| 374 | #define bfin_write_MDMAFLX1_XMODIFY_D(val) bfin_write16(MDMAFLX1_XMODIFY_D, val) |
| 375 | #define pMDMAFLX1_YCOUNT_D ((uint16_t volatile *)MDMAFLX1_YCOUNT_D) |
| 376 | #define bfin_read_MDMAFLX1_YCOUNT_D() bfin_read16(MDMAFLX1_YCOUNT_D) |
| 377 | #define bfin_write_MDMAFLX1_YCOUNT_D(val) bfin_write16(MDMAFLX1_YCOUNT_D, val) |
| 378 | #define pMDMAFLX1_YMODIFY_D ((uint16_t volatile *)MDMAFLX1_YMODIFY_D) |
| 379 | #define bfin_read_MDMAFLX1_YMODIFY_D() bfin_read16(MDMAFLX1_YMODIFY_D) |
| 380 | #define bfin_write_MDMAFLX1_YMODIFY_D(val) bfin_write16(MDMAFLX1_YMODIFY_D, val) |
| 381 | #define pMDMAFLX1_IRQSTAT_D ((uint16_t volatile *)MDMAFLX1_IRQSTAT_D) |
| 382 | #define bfin_read_MDMAFLX1_IRQSTAT_D() bfin_read16(MDMAFLX1_IRQSTAT_D) |
| 383 | #define bfin_write_MDMAFLX1_IRQSTAT_D(val) bfin_write16(MDMAFLX1_IRQSTAT_D, val) |
| 384 | #define pMDMAFLX1_PMAP_D ((uint16_t volatile *)MDMAFLX1_PMAP_D) |
| 385 | #define bfin_read_MDMAFLX1_PMAP_D() bfin_read16(MDMAFLX1_PMAP_D) |
| 386 | #define bfin_write_MDMAFLX1_PMAP_D(val) bfin_write16(MDMAFLX1_PMAP_D, val) |
| 387 | #define pMDMAFLX1_CURXCOUNT_D ((uint16_t volatile *)MDMAFLX1_CURXCOUNT_D) |
| 388 | #define bfin_read_MDMAFLX1_CURXCOUNT_D() bfin_read16(MDMAFLX1_CURXCOUNT_D) |
| 389 | #define bfin_write_MDMAFLX1_CURXCOUNT_D(val) bfin_write16(MDMAFLX1_CURXCOUNT_D, val) |
| 390 | #define pMDMAFLX1_CURYCOUNT_D ((uint16_t volatile *)MDMAFLX1_CURYCOUNT_D) |
| 391 | #define bfin_read_MDMAFLX1_CURYCOUNT_D() bfin_read16(MDMAFLX1_CURYCOUNT_D) |
| 392 | #define bfin_write_MDMAFLX1_CURYCOUNT_D(val) bfin_write16(MDMAFLX1_CURYCOUNT_D, val) |
| 393 | #define pMDMAFLX1_DMACNFG_S ((uint16_t volatile *)MDMAFLX1_DMACNFG_S) |
| 394 | #define bfin_read_MDMAFLX1_DMACNFG_S() bfin_read16(MDMAFLX1_DMACNFG_S) |
| 395 | #define bfin_write_MDMAFLX1_DMACNFG_S(val) bfin_write16(MDMAFLX1_DMACNFG_S, val) |
| 396 | #define pMDMAFLX1_XCOUNT_S ((uint16_t volatile *)MDMAFLX1_XCOUNT_S) |
| 397 | #define bfin_read_MDMAFLX1_XCOUNT_S() bfin_read16(MDMAFLX1_XCOUNT_S) |
| 398 | #define bfin_write_MDMAFLX1_XCOUNT_S(val) bfin_write16(MDMAFLX1_XCOUNT_S, val) |
| 399 | #define pMDMAFLX1_XMODIFY_S ((uint16_t volatile *)MDMAFLX1_XMODIFY_S) |
| 400 | #define bfin_read_MDMAFLX1_XMODIFY_S() bfin_read16(MDMAFLX1_XMODIFY_S) |
| 401 | #define bfin_write_MDMAFLX1_XMODIFY_S(val) bfin_write16(MDMAFLX1_XMODIFY_S, val) |
| 402 | #define pMDMAFLX1_YCOUNT_S ((uint16_t volatile *)MDMAFLX1_YCOUNT_S) |
| 403 | #define bfin_read_MDMAFLX1_YCOUNT_S() bfin_read16(MDMAFLX1_YCOUNT_S) |
| 404 | #define bfin_write_MDMAFLX1_YCOUNT_S(val) bfin_write16(MDMAFLX1_YCOUNT_S, val) |
| 405 | #define pMDMAFLX1_YMODIFY_S ((uint16_t volatile *)MDMAFLX1_YMODIFY_S) |
| 406 | #define bfin_read_MDMAFLX1_YMODIFY_S() bfin_read16(MDMAFLX1_YMODIFY_S) |
| 407 | #define bfin_write_MDMAFLX1_YMODIFY_S(val) bfin_write16(MDMAFLX1_YMODIFY_S, val) |
| 408 | #define pMDMAFLX1_IRQSTAT_S ((uint16_t volatile *)MDMAFLX1_IRQSTAT_S) |
| 409 | #define bfin_read_MDMAFLX1_IRQSTAT_S() bfin_read16(MDMAFLX1_IRQSTAT_S) |
| 410 | #define bfin_write_MDMAFLX1_IRQSTAT_S(val) bfin_write16(MDMAFLX1_IRQSTAT_S, val) |
| 411 | #define pMDMAFLX1_PMAP_S ((uint16_t volatile *)MDMAFLX1_PMAP_S) |
| 412 | #define bfin_read_MDMAFLX1_PMAP_S() bfin_read16(MDMAFLX1_PMAP_S) |
| 413 | #define bfin_write_MDMAFLX1_PMAP_S(val) bfin_write16(MDMAFLX1_PMAP_S, val) |
| 414 | #define pMDMAFLX1_CURXCOUNT_S ((uint16_t volatile *)MDMAFLX1_CURXCOUNT_S) |
| 415 | #define bfin_read_MDMAFLX1_CURXCOUNT_S() bfin_read16(MDMAFLX1_CURXCOUNT_S) |
| 416 | #define bfin_write_MDMAFLX1_CURXCOUNT_S(val) bfin_write16(MDMAFLX1_CURXCOUNT_S, val) |
| 417 | #define pMDMAFLX1_CURYCOUNT_S ((uint16_t volatile *)MDMAFLX1_CURYCOUNT_S) |
| 418 | #define bfin_read_MDMAFLX1_CURYCOUNT_S() bfin_read16(MDMAFLX1_CURYCOUNT_S) |
| 419 | #define bfin_write_MDMAFLX1_CURYCOUNT_S(val) bfin_write16(MDMAFLX1_CURYCOUNT_S, val) |
| 420 | #define pDMAFLX0_DMACNFG ((uint16_t volatile *)DMAFLX0_DMACNFG) |
| 421 | #define bfin_read_DMAFLX0_DMACNFG() bfin_read16(DMAFLX0_DMACNFG) |
| 422 | #define bfin_write_DMAFLX0_DMACNFG(val) bfin_write16(DMAFLX0_DMACNFG, val) |
| 423 | #define pDMAFLX0_XCOUNT ((uint16_t volatile *)DMAFLX0_XCOUNT) |
| 424 | #define bfin_read_DMAFLX0_XCOUNT() bfin_read16(DMAFLX0_XCOUNT) |
| 425 | #define bfin_write_DMAFLX0_XCOUNT(val) bfin_write16(DMAFLX0_XCOUNT, val) |
| 426 | #define pDMAFLX0_XMODIFY ((uint16_t volatile *)DMAFLX0_XMODIFY) |
| 427 | #define bfin_read_DMAFLX0_XMODIFY() bfin_read16(DMAFLX0_XMODIFY) |
| 428 | #define bfin_write_DMAFLX0_XMODIFY(val) bfin_write16(DMAFLX0_XMODIFY, val) |
| 429 | #define pDMAFLX0_YCOUNT ((uint16_t volatile *)DMAFLX0_YCOUNT) |
| 430 | #define bfin_read_DMAFLX0_YCOUNT() bfin_read16(DMAFLX0_YCOUNT) |
| 431 | #define bfin_write_DMAFLX0_YCOUNT(val) bfin_write16(DMAFLX0_YCOUNT, val) |
| 432 | #define pDMAFLX0_YMODIFY ((uint16_t volatile *)DMAFLX0_YMODIFY) |
| 433 | #define bfin_read_DMAFLX0_YMODIFY() bfin_read16(DMAFLX0_YMODIFY) |
| 434 | #define bfin_write_DMAFLX0_YMODIFY(val) bfin_write16(DMAFLX0_YMODIFY, val) |
| 435 | #define pDMAFLX0_IRQSTAT ((uint16_t volatile *)DMAFLX0_IRQSTAT) |
| 436 | #define bfin_read_DMAFLX0_IRQSTAT() bfin_read16(DMAFLX0_IRQSTAT) |
| 437 | #define bfin_write_DMAFLX0_IRQSTAT(val) bfin_write16(DMAFLX0_IRQSTAT, val) |
| 438 | #define pDMAFLX0_PMAP ((uint16_t volatile *)DMAFLX0_PMAP) |
| 439 | #define bfin_read_DMAFLX0_PMAP() bfin_read16(DMAFLX0_PMAP) |
| 440 | #define bfin_write_DMAFLX0_PMAP(val) bfin_write16(DMAFLX0_PMAP, val) |
| 441 | #define pDMAFLX0_CURXCOUNT ((uint16_t volatile *)DMAFLX0_CURXCOUNT) |
| 442 | #define bfin_read_DMAFLX0_CURXCOUNT() bfin_read16(DMAFLX0_CURXCOUNT) |
| 443 | #define bfin_write_DMAFLX0_CURXCOUNT(val) bfin_write16(DMAFLX0_CURXCOUNT, val) |
| 444 | #define pDMAFLX0_CURYCOUNT ((uint16_t volatile *)DMAFLX0_CURYCOUNT) |
| 445 | #define bfin_read_DMAFLX0_CURYCOUNT() bfin_read16(DMAFLX0_CURYCOUNT) |
| 446 | #define bfin_write_DMAFLX0_CURYCOUNT(val) bfin_write16(DMAFLX0_CURYCOUNT, val) |
| 447 | #define pDMAFLX1_DMACNFG ((uint16_t volatile *)DMAFLX1_DMACNFG) |
| 448 | #define bfin_read_DMAFLX1_DMACNFG() bfin_read16(DMAFLX1_DMACNFG) |
| 449 | #define bfin_write_DMAFLX1_DMACNFG(val) bfin_write16(DMAFLX1_DMACNFG, val) |
| 450 | #define pDMAFLX1_XCOUNT ((uint16_t volatile *)DMAFLX1_XCOUNT) |
| 451 | #define bfin_read_DMAFLX1_XCOUNT() bfin_read16(DMAFLX1_XCOUNT) |
| 452 | #define bfin_write_DMAFLX1_XCOUNT(val) bfin_write16(DMAFLX1_XCOUNT, val) |
| 453 | #define pDMAFLX1_XMODIFY ((uint16_t volatile *)DMAFLX1_XMODIFY) |
| 454 | #define bfin_read_DMAFLX1_XMODIFY() bfin_read16(DMAFLX1_XMODIFY) |
| 455 | #define bfin_write_DMAFLX1_XMODIFY(val) bfin_write16(DMAFLX1_XMODIFY, val) |
| 456 | #define pDMAFLX1_YCOUNT ((uint16_t volatile *)DMAFLX1_YCOUNT) |
| 457 | #define bfin_read_DMAFLX1_YCOUNT() bfin_read16(DMAFLX1_YCOUNT) |
| 458 | #define bfin_write_DMAFLX1_YCOUNT(val) bfin_write16(DMAFLX1_YCOUNT, val) |
| 459 | #define pDMAFLX1_YMODIFY ((uint16_t volatile *)DMAFLX1_YMODIFY) |
| 460 | #define bfin_read_DMAFLX1_YMODIFY() bfin_read16(DMAFLX1_YMODIFY) |
| 461 | #define bfin_write_DMAFLX1_YMODIFY(val) bfin_write16(DMAFLX1_YMODIFY, val) |
| 462 | #define pDMAFLX1_IRQSTAT ((uint16_t volatile *)DMAFLX1_IRQSTAT) |
| 463 | #define bfin_read_DMAFLX1_IRQSTAT() bfin_read16(DMAFLX1_IRQSTAT) |
| 464 | #define bfin_write_DMAFLX1_IRQSTAT(val) bfin_write16(DMAFLX1_IRQSTAT, val) |
| 465 | #define pDMAFLX1_PMAP ((uint16_t volatile *)DMAFLX1_PMAP) |
| 466 | #define bfin_read_DMAFLX1_PMAP() bfin_read16(DMAFLX1_PMAP) |
| 467 | #define bfin_write_DMAFLX1_PMAP(val) bfin_write16(DMAFLX1_PMAP, val) |
| 468 | #define pDMAFLX1_CURXCOUNT ((uint16_t volatile *)DMAFLX1_CURXCOUNT) |
| 469 | #define bfin_read_DMAFLX1_CURXCOUNT() bfin_read16(DMAFLX1_CURXCOUNT) |
| 470 | #define bfin_write_DMAFLX1_CURXCOUNT(val) bfin_write16(DMAFLX1_CURXCOUNT, val) |
| 471 | #define pDMAFLX1_CURYCOUNT ((uint16_t volatile *)DMAFLX1_CURYCOUNT) |
| 472 | #define bfin_read_DMAFLX1_CURYCOUNT() bfin_read16(DMAFLX1_CURYCOUNT) |
| 473 | #define bfin_write_DMAFLX1_CURYCOUNT(val) bfin_write16(DMAFLX1_CURYCOUNT, val) |
| 474 | #define pDMAFLX2_DMACNFG ((uint16_t volatile *)DMAFLX2_DMACNFG) |
| 475 | #define bfin_read_DMAFLX2_DMACNFG() bfin_read16(DMAFLX2_DMACNFG) |
| 476 | #define bfin_write_DMAFLX2_DMACNFG(val) bfin_write16(DMAFLX2_DMACNFG, val) |
| 477 | #define pDMAFLX2_XCOUNT ((uint16_t volatile *)DMAFLX2_XCOUNT) |
| 478 | #define bfin_read_DMAFLX2_XCOUNT() bfin_read16(DMAFLX2_XCOUNT) |
| 479 | #define bfin_write_DMAFLX2_XCOUNT(val) bfin_write16(DMAFLX2_XCOUNT, val) |
| 480 | #define pDMAFLX2_XMODIFY ((uint16_t volatile *)DMAFLX2_XMODIFY) |
| 481 | #define bfin_read_DMAFLX2_XMODIFY() bfin_read16(DMAFLX2_XMODIFY) |
| 482 | #define bfin_write_DMAFLX2_XMODIFY(val) bfin_write16(DMAFLX2_XMODIFY, val) |
| 483 | #define pDMAFLX2_YCOUNT ((uint16_t volatile *)DMAFLX2_YCOUNT) |
| 484 | #define bfin_read_DMAFLX2_YCOUNT() bfin_read16(DMAFLX2_YCOUNT) |
| 485 | #define bfin_write_DMAFLX2_YCOUNT(val) bfin_write16(DMAFLX2_YCOUNT, val) |
| 486 | #define pDMAFLX2_YMODIFY ((uint16_t volatile *)DMAFLX2_YMODIFY) |
| 487 | #define bfin_read_DMAFLX2_YMODIFY() bfin_read16(DMAFLX2_YMODIFY) |
| 488 | #define bfin_write_DMAFLX2_YMODIFY(val) bfin_write16(DMAFLX2_YMODIFY, val) |
| 489 | #define pDMAFLX2_IRQSTAT ((uint16_t volatile *)DMAFLX2_IRQSTAT) |
| 490 | #define bfin_read_DMAFLX2_IRQSTAT() bfin_read16(DMAFLX2_IRQSTAT) |
| 491 | #define bfin_write_DMAFLX2_IRQSTAT(val) bfin_write16(DMAFLX2_IRQSTAT, val) |
| 492 | #define pDMAFLX2_PMAP ((uint16_t volatile *)DMAFLX2_PMAP) |
| 493 | #define bfin_read_DMAFLX2_PMAP() bfin_read16(DMAFLX2_PMAP) |
| 494 | #define bfin_write_DMAFLX2_PMAP(val) bfin_write16(DMAFLX2_PMAP, val) |
| 495 | #define pDMAFLX2_CURXCOUNT ((uint16_t volatile *)DMAFLX2_CURXCOUNT) |
| 496 | #define bfin_read_DMAFLX2_CURXCOUNT() bfin_read16(DMAFLX2_CURXCOUNT) |
| 497 | #define bfin_write_DMAFLX2_CURXCOUNT(val) bfin_write16(DMAFLX2_CURXCOUNT, val) |
| 498 | #define pDMAFLX2_CURYCOUNT ((uint16_t volatile *)DMAFLX2_CURYCOUNT) |
| 499 | #define bfin_read_DMAFLX2_CURYCOUNT() bfin_read16(DMAFLX2_CURYCOUNT) |
| 500 | #define bfin_write_DMAFLX2_CURYCOUNT(val) bfin_write16(DMAFLX2_CURYCOUNT, val) |
| 501 | #define pDMAFLX3_DMACNFG ((uint16_t volatile *)DMAFLX3_DMACNFG) |
| 502 | #define bfin_read_DMAFLX3_DMACNFG() bfin_read16(DMAFLX3_DMACNFG) |
| 503 | #define bfin_write_DMAFLX3_DMACNFG(val) bfin_write16(DMAFLX3_DMACNFG, val) |
| 504 | #define pDMAFLX3_XCOUNT ((uint16_t volatile *)DMAFLX3_XCOUNT) |
| 505 | #define bfin_read_DMAFLX3_XCOUNT() bfin_read16(DMAFLX3_XCOUNT) |
| 506 | #define bfin_write_DMAFLX3_XCOUNT(val) bfin_write16(DMAFLX3_XCOUNT, val) |
| 507 | #define pDMAFLX3_XMODIFY ((uint16_t volatile *)DMAFLX3_XMODIFY) |
| 508 | #define bfin_read_DMAFLX3_XMODIFY() bfin_read16(DMAFLX3_XMODIFY) |
| 509 | #define bfin_write_DMAFLX3_XMODIFY(val) bfin_write16(DMAFLX3_XMODIFY, val) |
| 510 | #define pDMAFLX3_YCOUNT ((uint16_t volatile *)DMAFLX3_YCOUNT) |
| 511 | #define bfin_read_DMAFLX3_YCOUNT() bfin_read16(DMAFLX3_YCOUNT) |
| 512 | #define bfin_write_DMAFLX3_YCOUNT(val) bfin_write16(DMAFLX3_YCOUNT, val) |
| 513 | #define pDMAFLX3_YMODIFY ((uint16_t volatile *)DMAFLX3_YMODIFY) |
| 514 | #define bfin_read_DMAFLX3_YMODIFY() bfin_read16(DMAFLX3_YMODIFY) |
| 515 | #define bfin_write_DMAFLX3_YMODIFY(val) bfin_write16(DMAFLX3_YMODIFY, val) |
| 516 | #define pDMAFLX3_IRQSTAT ((uint16_t volatile *)DMAFLX3_IRQSTAT) |
| 517 | #define bfin_read_DMAFLX3_IRQSTAT() bfin_read16(DMAFLX3_IRQSTAT) |
| 518 | #define bfin_write_DMAFLX3_IRQSTAT(val) bfin_write16(DMAFLX3_IRQSTAT, val) |
| 519 | #define pDMAFLX3_PMAP ((uint16_t volatile *)DMAFLX3_PMAP) |
| 520 | #define bfin_read_DMAFLX3_PMAP() bfin_read16(DMAFLX3_PMAP) |
| 521 | #define bfin_write_DMAFLX3_PMAP(val) bfin_write16(DMAFLX3_PMAP, val) |
| 522 | #define pDMAFLX3_CURXCOUNT ((uint16_t volatile *)DMAFLX3_CURXCOUNT) |
| 523 | #define bfin_read_DMAFLX3_CURXCOUNT() bfin_read16(DMAFLX3_CURXCOUNT) |
| 524 | #define bfin_write_DMAFLX3_CURXCOUNT(val) bfin_write16(DMAFLX3_CURXCOUNT, val) |
| 525 | #define pDMAFLX3_CURYCOUNT ((uint16_t volatile *)DMAFLX3_CURYCOUNT) |
| 526 | #define bfin_read_DMAFLX3_CURYCOUNT() bfin_read16(DMAFLX3_CURYCOUNT) |
| 527 | #define bfin_write_DMAFLX3_CURYCOUNT(val) bfin_write16(DMAFLX3_CURYCOUNT, val) |
| 528 | #define pDMAFLX4_DMACNFG ((uint16_t volatile *)DMAFLX4_DMACNFG) |
| 529 | #define bfin_read_DMAFLX4_DMACNFG() bfin_read16(DMAFLX4_DMACNFG) |
| 530 | #define bfin_write_DMAFLX4_DMACNFG(val) bfin_write16(DMAFLX4_DMACNFG, val) |
| 531 | #define pDMAFLX4_XCOUNT ((uint16_t volatile *)DMAFLX4_XCOUNT) |
| 532 | #define bfin_read_DMAFLX4_XCOUNT() bfin_read16(DMAFLX4_XCOUNT) |
| 533 | #define bfin_write_DMAFLX4_XCOUNT(val) bfin_write16(DMAFLX4_XCOUNT, val) |
| 534 | #define pDMAFLX4_XMODIFY ((uint16_t volatile *)DMAFLX4_XMODIFY) |
| 535 | #define bfin_read_DMAFLX4_XMODIFY() bfin_read16(DMAFLX4_XMODIFY) |
| 536 | #define bfin_write_DMAFLX4_XMODIFY(val) bfin_write16(DMAFLX4_XMODIFY, val) |
| 537 | #define pDMAFLX4_YCOUNT ((uint16_t volatile *)DMAFLX4_YCOUNT) |
| 538 | #define bfin_read_DMAFLX4_YCOUNT() bfin_read16(DMAFLX4_YCOUNT) |
| 539 | #define bfin_write_DMAFLX4_YCOUNT(val) bfin_write16(DMAFLX4_YCOUNT, val) |
| 540 | #define pDMAFLX4_YMODIFY ((uint16_t volatile *)DMAFLX4_YMODIFY) |
| 541 | #define bfin_read_DMAFLX4_YMODIFY() bfin_read16(DMAFLX4_YMODIFY) |
| 542 | #define bfin_write_DMAFLX4_YMODIFY(val) bfin_write16(DMAFLX4_YMODIFY, val) |
| 543 | #define pDMAFLX4_IRQSTAT ((uint16_t volatile *)DMAFLX4_IRQSTAT) |
| 544 | #define bfin_read_DMAFLX4_IRQSTAT() bfin_read16(DMAFLX4_IRQSTAT) |
| 545 | #define bfin_write_DMAFLX4_IRQSTAT(val) bfin_write16(DMAFLX4_IRQSTAT, val) |
| 546 | #define pDMAFLX4_PMAP ((uint16_t volatile *)DMAFLX4_PMAP) |
| 547 | #define bfin_read_DMAFLX4_PMAP() bfin_read16(DMAFLX4_PMAP) |
| 548 | #define bfin_write_DMAFLX4_PMAP(val) bfin_write16(DMAFLX4_PMAP, val) |
| 549 | #define pDMAFLX4_CURXCOUNT ((uint16_t volatile *)DMAFLX4_CURXCOUNT) |
| 550 | #define bfin_read_DMAFLX4_CURXCOUNT() bfin_read16(DMAFLX4_CURXCOUNT) |
| 551 | #define bfin_write_DMAFLX4_CURXCOUNT(val) bfin_write16(DMAFLX4_CURXCOUNT, val) |
| 552 | #define pDMAFLX4_CURYCOUNT ((uint16_t volatile *)DMAFLX4_CURYCOUNT) |
| 553 | #define bfin_read_DMAFLX4_CURYCOUNT() bfin_read16(DMAFLX4_CURYCOUNT) |
| 554 | #define bfin_write_DMAFLX4_CURYCOUNT(val) bfin_write16(DMAFLX4_CURYCOUNT, val) |
| 555 | #define pDMAFLX5_DMACNFG ((uint16_t volatile *)DMAFLX5_DMACNFG) |
| 556 | #define bfin_read_DMAFLX5_DMACNFG() bfin_read16(DMAFLX5_DMACNFG) |
| 557 | #define bfin_write_DMAFLX5_DMACNFG(val) bfin_write16(DMAFLX5_DMACNFG, val) |
| 558 | #define pDMAFLX5_XCOUNT ((uint16_t volatile *)DMAFLX5_XCOUNT) |
| 559 | #define bfin_read_DMAFLX5_XCOUNT() bfin_read16(DMAFLX5_XCOUNT) |
| 560 | #define bfin_write_DMAFLX5_XCOUNT(val) bfin_write16(DMAFLX5_XCOUNT, val) |
| 561 | #define pDMAFLX5_XMODIFY ((uint16_t volatile *)DMAFLX5_XMODIFY) |
| 562 | #define bfin_read_DMAFLX5_XMODIFY() bfin_read16(DMAFLX5_XMODIFY) |
| 563 | #define bfin_write_DMAFLX5_XMODIFY(val) bfin_write16(DMAFLX5_XMODIFY, val) |
| 564 | #define pDMAFLX5_YCOUNT ((uint16_t volatile *)DMAFLX5_YCOUNT) |
| 565 | #define bfin_read_DMAFLX5_YCOUNT() bfin_read16(DMAFLX5_YCOUNT) |
| 566 | #define bfin_write_DMAFLX5_YCOUNT(val) bfin_write16(DMAFLX5_YCOUNT, val) |
| 567 | #define pDMAFLX5_YMODIFY ((uint16_t volatile *)DMAFLX5_YMODIFY) |
| 568 | #define bfin_read_DMAFLX5_YMODIFY() bfin_read16(DMAFLX5_YMODIFY) |
| 569 | #define bfin_write_DMAFLX5_YMODIFY(val) bfin_write16(DMAFLX5_YMODIFY, val) |
| 570 | #define pDMAFLX5_IRQSTAT ((uint16_t volatile *)DMAFLX5_IRQSTAT) |
| 571 | #define bfin_read_DMAFLX5_IRQSTAT() bfin_read16(DMAFLX5_IRQSTAT) |
| 572 | #define bfin_write_DMAFLX5_IRQSTAT(val) bfin_write16(DMAFLX5_IRQSTAT, val) |
| 573 | #define pDMAFLX5_PMAP ((uint16_t volatile *)DMAFLX5_PMAP) |
| 574 | #define bfin_read_DMAFLX5_PMAP() bfin_read16(DMAFLX5_PMAP) |
| 575 | #define bfin_write_DMAFLX5_PMAP(val) bfin_write16(DMAFLX5_PMAP, val) |
| 576 | #define pDMAFLX5_CURXCOUNT ((uint16_t volatile *)DMAFLX5_CURXCOUNT) |
| 577 | #define bfin_read_DMAFLX5_CURXCOUNT() bfin_read16(DMAFLX5_CURXCOUNT) |
| 578 | #define bfin_write_DMAFLX5_CURXCOUNT(val) bfin_write16(DMAFLX5_CURXCOUNT, val) |
| 579 | #define pDMAFLX5_CURYCOUNT ((uint16_t volatile *)DMAFLX5_CURYCOUNT) |
| 580 | #define bfin_read_DMAFLX5_CURYCOUNT() bfin_read16(DMAFLX5_CURYCOUNT) |
| 581 | #define bfin_write_DMAFLX5_CURYCOUNT(val) bfin_write16(DMAFLX5_CURYCOUNT, val) |
| 582 | #define pDMAFLX6_DMACNFG ((uint16_t volatile *)DMAFLX6_DMACNFG) |
| 583 | #define bfin_read_DMAFLX6_DMACNFG() bfin_read16(DMAFLX6_DMACNFG) |
| 584 | #define bfin_write_DMAFLX6_DMACNFG(val) bfin_write16(DMAFLX6_DMACNFG, val) |
| 585 | #define pDMAFLX6_XCOUNT ((uint16_t volatile *)DMAFLX6_XCOUNT) |
| 586 | #define bfin_read_DMAFLX6_XCOUNT() bfin_read16(DMAFLX6_XCOUNT) |
| 587 | #define bfin_write_DMAFLX6_XCOUNT(val) bfin_write16(DMAFLX6_XCOUNT, val) |
| 588 | #define pDMAFLX6_XMODIFY ((uint16_t volatile *)DMAFLX6_XMODIFY) |
| 589 | #define bfin_read_DMAFLX6_XMODIFY() bfin_read16(DMAFLX6_XMODIFY) |
| 590 | #define bfin_write_DMAFLX6_XMODIFY(val) bfin_write16(DMAFLX6_XMODIFY, val) |
| 591 | #define pDMAFLX6_YCOUNT ((uint16_t volatile *)DMAFLX6_YCOUNT) |
| 592 | #define bfin_read_DMAFLX6_YCOUNT() bfin_read16(DMAFLX6_YCOUNT) |
| 593 | #define bfin_write_DMAFLX6_YCOUNT(val) bfin_write16(DMAFLX6_YCOUNT, val) |
| 594 | #define pDMAFLX6_YMODIFY ((uint16_t volatile *)DMAFLX6_YMODIFY) |
| 595 | #define bfin_read_DMAFLX6_YMODIFY() bfin_read16(DMAFLX6_YMODIFY) |
| 596 | #define bfin_write_DMAFLX6_YMODIFY(val) bfin_write16(DMAFLX6_YMODIFY, val) |
| 597 | #define pDMAFLX6_IRQSTAT ((uint16_t volatile *)DMAFLX6_IRQSTAT) |
| 598 | #define bfin_read_DMAFLX6_IRQSTAT() bfin_read16(DMAFLX6_IRQSTAT) |
| 599 | #define bfin_write_DMAFLX6_IRQSTAT(val) bfin_write16(DMAFLX6_IRQSTAT, val) |
| 600 | #define pDMAFLX6_PMAP ((uint16_t volatile *)DMAFLX6_PMAP) |
| 601 | #define bfin_read_DMAFLX6_PMAP() bfin_read16(DMAFLX6_PMAP) |
| 602 | #define bfin_write_DMAFLX6_PMAP(val) bfin_write16(DMAFLX6_PMAP, val) |
| 603 | #define pDMAFLX6_CURXCOUNT ((uint16_t volatile *)DMAFLX6_CURXCOUNT) |
| 604 | #define bfin_read_DMAFLX6_CURXCOUNT() bfin_read16(DMAFLX6_CURXCOUNT) |
| 605 | #define bfin_write_DMAFLX6_CURXCOUNT(val) bfin_write16(DMAFLX6_CURXCOUNT, val) |
| 606 | #define pDMAFLX6_CURYCOUNT ((uint16_t volatile *)DMAFLX6_CURYCOUNT) |
| 607 | #define bfin_read_DMAFLX6_CURYCOUNT() bfin_read16(DMAFLX6_CURYCOUNT) |
| 608 | #define bfin_write_DMAFLX6_CURYCOUNT(val) bfin_write16(DMAFLX6_CURYCOUNT, val) |
| 609 | #define pDMAFLX7_DMACNFG ((uint16_t volatile *)DMAFLX7_DMACNFG) |
| 610 | #define bfin_read_DMAFLX7_DMACNFG() bfin_read16(DMAFLX7_DMACNFG) |
| 611 | #define bfin_write_DMAFLX7_DMACNFG(val) bfin_write16(DMAFLX7_DMACNFG, val) |
| 612 | #define pDMAFLX7_XCOUNT ((uint16_t volatile *)DMAFLX7_XCOUNT) |
| 613 | #define bfin_read_DMAFLX7_XCOUNT() bfin_read16(DMAFLX7_XCOUNT) |
| 614 | #define bfin_write_DMAFLX7_XCOUNT(val) bfin_write16(DMAFLX7_XCOUNT, val) |
| 615 | #define pDMAFLX7_XMODIFY ((uint16_t volatile *)DMAFLX7_XMODIFY) |
| 616 | #define bfin_read_DMAFLX7_XMODIFY() bfin_read16(DMAFLX7_XMODIFY) |
| 617 | #define bfin_write_DMAFLX7_XMODIFY(val) bfin_write16(DMAFLX7_XMODIFY, val) |
| 618 | #define pDMAFLX7_YCOUNT ((uint16_t volatile *)DMAFLX7_YCOUNT) |
| 619 | #define bfin_read_DMAFLX7_YCOUNT() bfin_read16(DMAFLX7_YCOUNT) |
| 620 | #define bfin_write_DMAFLX7_YCOUNT(val) bfin_write16(DMAFLX7_YCOUNT, val) |
| 621 | #define pDMAFLX7_YMODIFY ((uint16_t volatile *)DMAFLX7_YMODIFY) |
| 622 | #define bfin_read_DMAFLX7_YMODIFY() bfin_read16(DMAFLX7_YMODIFY) |
| 623 | #define bfin_write_DMAFLX7_YMODIFY(val) bfin_write16(DMAFLX7_YMODIFY, val) |
| 624 | #define pDMAFLX7_IRQSTAT ((uint16_t volatile *)DMAFLX7_IRQSTAT) |
| 625 | #define bfin_read_DMAFLX7_IRQSTAT() bfin_read16(DMAFLX7_IRQSTAT) |
| 626 | #define bfin_write_DMAFLX7_IRQSTAT(val) bfin_write16(DMAFLX7_IRQSTAT, val) |
| 627 | #define pDMAFLX7_PMAP ((uint16_t volatile *)DMAFLX7_PMAP) |
| 628 | #define bfin_read_DMAFLX7_PMAP() bfin_read16(DMAFLX7_PMAP) |
| 629 | #define bfin_write_DMAFLX7_PMAP(val) bfin_write16(DMAFLX7_PMAP, val) |
| 630 | #define pDMAFLX7_CURXCOUNT ((uint16_t volatile *)DMAFLX7_CURXCOUNT) |
| 631 | #define bfin_read_DMAFLX7_CURXCOUNT() bfin_read16(DMAFLX7_CURXCOUNT) |
| 632 | #define bfin_write_DMAFLX7_CURXCOUNT(val) bfin_write16(DMAFLX7_CURXCOUNT, val) |
| 633 | #define pDMAFLX7_CURYCOUNT ((uint16_t volatile *)DMAFLX7_CURYCOUNT) |
| 634 | #define bfin_read_DMAFLX7_CURYCOUNT() bfin_read16(DMAFLX7_CURYCOUNT) |
| 635 | #define bfin_write_DMAFLX7_CURYCOUNT(val) bfin_write16(DMAFLX7_CURYCOUNT, val) |
| 636 | #define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) |
| 637 | #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) |
| 638 | #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) |
| 639 | #define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) |
| 640 | #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) |
| 641 | #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) |
| 642 | #define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) |
| 643 | #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) |
| 644 | #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) |
| 645 | #define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) |
| 646 | #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) |
| 647 | #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) |
| 648 | #define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) |
| 649 | #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) |
| 650 | #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) |
| 651 | #define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) |
| 652 | #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) |
| 653 | #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) |
| 654 | #define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) |
| 655 | #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) |
| 656 | #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) |
| 657 | #define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) |
| 658 | #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) |
| 659 | #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) |
| 660 | #define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) |
| 661 | #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) |
| 662 | #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) |
| 663 | #define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) |
| 664 | #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) |
| 665 | #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) |
| 666 | #define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) |
| 667 | #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) |
| 668 | #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) |
| 669 | #define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) |
| 670 | #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) |
| 671 | #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) |
| 672 | #define pTIMER_ENABLE ((uint16_t volatile *)TIMER_ENABLE) |
| 673 | #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) |
| 674 | #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) |
| 675 | #define pTIMER_DISABLE ((uint16_t volatile *)TIMER_DISABLE) |
| 676 | #define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) |
| 677 | #define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) |
| 678 | #define pTIMER_STATUS ((uint16_t volatile *)TIMER_STATUS) |
| 679 | #define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS) |
| 680 | #define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS, val) |
| 681 | #define pSIC_RVECT ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */ |
| 682 | #define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) |
| 683 | #define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val) |
| 684 | #define pSIC_IMASK ((uint32_t volatile *)SIC_IMASK) /* Interrupt Mask Register */ |
| 685 | #define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) |
| 686 | #define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val) |
| 687 | #define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */ |
| 688 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) |
| 689 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) |
| 690 | #define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */ |
| 691 | #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) |
| 692 | #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) |
| 693 | #define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */ |
| 694 | #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) |
| 695 | #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) |
| 696 | #define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */ |
| 697 | #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) |
| 698 | #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) |
| 699 | #define pSIC_ISR ((uint32_t volatile *)SIC_ISR) /* Interrupt Status Register */ |
| 700 | #define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) |
| 701 | #define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val) |
| 702 | #define pSIC_IWR ((uint32_t volatile *)SIC_IWR) /* Interrupt Wakeup Register */ |
| 703 | #define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) |
| 704 | #define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val) |
| 705 | #define pUART_THR ((uint16_t volatile *)UART_THR) /* Transmit Holding */ |
| 706 | #define bfin_read_UART_THR() bfin_read16(UART_THR) |
| 707 | #define bfin_write_UART_THR(val) bfin_write16(UART_THR, val) |
| 708 | #define pUART_DLL ((uint16_t volatile *)UART_DLL) /* Divisor Latch Low Byte */ |
| 709 | #define bfin_read_UART_DLL() bfin_read16(UART_DLL) |
| 710 | #define bfin_write_UART_DLL(val) bfin_write16(UART_DLL, val) |
| 711 | #define pUART_DLH ((uint16_t volatile *)UART_DLH) /* Divisor Latch High Byte */ |
| 712 | #define bfin_read_UART_DLH() bfin_read16(UART_DLH) |
| 713 | #define bfin_write_UART_DLH(val) bfin_write16(UART_DLH, val) |
| 714 | #define pUART_IER ((uint16_t volatile *)UART_IER) |
| 715 | #define bfin_read_UART_IER() bfin_read16(UART_IER) |
| 716 | #define bfin_write_UART_IER(val) bfin_write16(UART_IER, val) |
| 717 | #define pUART_IIR ((uint16_t volatile *)UART_IIR) |
| 718 | #define bfin_read_UART_IIR() bfin_read16(UART_IIR) |
| 719 | #define bfin_write_UART_IIR(val) bfin_write16(UART_IIR, val) |
| 720 | #define pUART_LCR ((uint16_t volatile *)UART_LCR) |
| 721 | #define bfin_read_UART_LCR() bfin_read16(UART_LCR) |
| 722 | #define bfin_write_UART_LCR(val) bfin_write16(UART_LCR, val) |
| 723 | #define pUART_MCR ((uint16_t volatile *)UART_MCR) |
| 724 | #define bfin_read_UART_MCR() bfin_read16(UART_MCR) |
| 725 | #define bfin_write_UART_MCR(val) bfin_write16(UART_MCR, val) |
| 726 | #define pUART_LSR ((uint16_t volatile *)UART_LSR) |
| 727 | #define bfin_read_UART_LSR() bfin_read16(UART_LSR) |
| 728 | #define bfin_write_UART_LSR(val) bfin_write16(UART_LSR, val) |
| 729 | #define pUART_SCR ((uint16_t volatile *)UART_SCR) |
| 730 | #define bfin_read_UART_SCR() bfin_read16(UART_SCR) |
| 731 | #define bfin_write_UART_SCR(val) bfin_write16(UART_SCR, val) |
| 732 | #define pUART_RBR ((uint16_t volatile *)UART_RBR) /* Receive Buffer */ |
| 733 | #define bfin_read_UART_RBR() bfin_read16(UART_RBR) |
| 734 | #define bfin_write_UART_RBR(val) bfin_write16(UART_RBR, val) |
| 735 | #define pUART_GCTL ((uint16_t volatile *)UART_GCTL) |
| 736 | #define bfin_read_UART_GCTL() bfin_read16(UART_GCTL) |
| 737 | #define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL, val) |
| 738 | #define pSPT0_TX_CONFIG0 ((uint16_t volatile *)SPT0_TX_CONFIG0) |
| 739 | #define bfin_read_SPT0_TX_CONFIG0() bfin_read16(SPT0_TX_CONFIG0) |
| 740 | #define bfin_write_SPT0_TX_CONFIG0(val) bfin_write16(SPT0_TX_CONFIG0, val) |
| 741 | #define pSPT0_TX_CONFIG1 ((uint16_t volatile *)SPT0_TX_CONFIG1) |
| 742 | #define bfin_read_SPT0_TX_CONFIG1() bfin_read16(SPT0_TX_CONFIG1) |
| 743 | #define bfin_write_SPT0_TX_CONFIG1(val) bfin_write16(SPT0_TX_CONFIG1, val) |
| 744 | #define pSPT0_RX_CONFIG0 ((uint16_t volatile *)SPT0_RX_CONFIG0) |
| 745 | #define bfin_read_SPT0_RX_CONFIG0() bfin_read16(SPT0_RX_CONFIG0) |
| 746 | #define bfin_write_SPT0_RX_CONFIG0(val) bfin_write16(SPT0_RX_CONFIG0, val) |
| 747 | #define pSPT0_RX_CONFIG1 ((uint16_t volatile *)SPT0_RX_CONFIG1) |
| 748 | #define bfin_read_SPT0_RX_CONFIG1() bfin_read16(SPT0_RX_CONFIG1) |
| 749 | #define bfin_write_SPT0_RX_CONFIG1(val) bfin_write16(SPT0_RX_CONFIG1, val) |
| 750 | #define pSPT0_TX ((uint32_t volatile *)SPT0_TX) |
| 751 | #define bfin_read_SPT0_TX() bfin_read32(SPT0_TX) |
| 752 | #define bfin_write_SPT0_TX(val) bfin_write32(SPT0_TX, val) |
| 753 | #define pSPT0_RX ((uint32_t volatile *)SPT0_RX) |
| 754 | #define bfin_read_SPT0_RX() bfin_read32(SPT0_RX) |
| 755 | #define bfin_write_SPT0_RX(val) bfin_write32(SPT0_RX, val) |
| 756 | #define pSPT0_TSCLKDIV ((uint16_t volatile *)SPT0_TSCLKDIV) |
| 757 | #define bfin_read_SPT0_TSCLKDIV() bfin_read16(SPT0_TSCLKDIV) |
| 758 | #define bfin_write_SPT0_TSCLKDIV(val) bfin_write16(SPT0_TSCLKDIV, val) |
| 759 | #define pSPT0_RSCLKDIV ((uint16_t volatile *)SPT0_RSCLKDIV) |
| 760 | #define bfin_read_SPT0_RSCLKDIV() bfin_read16(SPT0_RSCLKDIV) |
| 761 | #define bfin_write_SPT0_RSCLKDIV(val) bfin_write16(SPT0_RSCLKDIV, val) |
| 762 | #define pSPT0_TFSDIV ((uint16_t volatile *)SPT0_TFSDIV) |
| 763 | #define bfin_read_SPT0_TFSDIV() bfin_read16(SPT0_TFSDIV) |
| 764 | #define bfin_write_SPT0_TFSDIV(val) bfin_write16(SPT0_TFSDIV, val) |
| 765 | #define pSPT0_RFSDIV ((uint16_t volatile *)SPT0_RFSDIV) |
| 766 | #define bfin_read_SPT0_RFSDIV() bfin_read16(SPT0_RFSDIV) |
| 767 | #define bfin_write_SPT0_RFSDIV(val) bfin_write16(SPT0_RFSDIV, val) |
| 768 | #define pSPT0_STAT ((uint16_t volatile *)SPT0_STAT) |
| 769 | #define bfin_read_SPT0_STAT() bfin_read16(SPT0_STAT) |
| 770 | #define bfin_write_SPT0_STAT(val) bfin_write16(SPT0_STAT, val) |
| 771 | #define pSPT0_MTCS0 ((uint32_t volatile *)SPT0_MTCS0) |
| 772 | #define bfin_read_SPT0_MTCS0() bfin_read32(SPT0_MTCS0) |
| 773 | #define bfin_write_SPT0_MTCS0(val) bfin_write32(SPT0_MTCS0, val) |
| 774 | #define pSPT0_MTCS1 ((uint32_t volatile *)SPT0_MTCS1) |
| 775 | #define bfin_read_SPT0_MTCS1() bfin_read32(SPT0_MTCS1) |
| 776 | #define bfin_write_SPT0_MTCS1(val) bfin_write32(SPT0_MTCS1, val) |
| 777 | #define pSPT0_MTCS2 ((uint32_t volatile *)SPT0_MTCS2) |
| 778 | #define bfin_read_SPT0_MTCS2() bfin_read32(SPT0_MTCS2) |
| 779 | #define bfin_write_SPT0_MTCS2(val) bfin_write32(SPT0_MTCS2, val) |
| 780 | #define pSPT0_MTCS3 ((uint32_t volatile *)SPT0_MTCS3) |
| 781 | #define bfin_read_SPT0_MTCS3() bfin_read32(SPT0_MTCS3) |
| 782 | #define bfin_write_SPT0_MTCS3(val) bfin_write32(SPT0_MTCS3, val) |
| 783 | #define pSPT0_MRCS0 ((uint32_t volatile *)SPT0_MRCS0) |
| 784 | #define bfin_read_SPT0_MRCS0() bfin_read32(SPT0_MRCS0) |
| 785 | #define bfin_write_SPT0_MRCS0(val) bfin_write32(SPT0_MRCS0, val) |
| 786 | #define pSPT0_MRCS1 ((uint32_t volatile *)SPT0_MRCS1) |
| 787 | #define bfin_read_SPT0_MRCS1() bfin_read32(SPT0_MRCS1) |
| 788 | #define bfin_write_SPT0_MRCS1(val) bfin_write32(SPT0_MRCS1, val) |
| 789 | #define pSPT0_MRCS2 ((uint32_t volatile *)SPT0_MRCS2) |
| 790 | #define bfin_read_SPT0_MRCS2() bfin_read32(SPT0_MRCS2) |
| 791 | #define bfin_write_SPT0_MRCS2(val) bfin_write32(SPT0_MRCS2, val) |
| 792 | #define pSPT0_MRCS3 ((uint32_t volatile *)SPT0_MRCS3) |
| 793 | #define bfin_read_SPT0_MRCS3() bfin_read32(SPT0_MRCS3) |
| 794 | #define bfin_write_SPT0_MRCS3(val) bfin_write32(SPT0_MRCS3, val) |
| 795 | #define pSPT0_MCMC1 ((uint16_t volatile *)SPT0_MCMC1) |
| 796 | #define bfin_read_SPT0_MCMC1() bfin_read16(SPT0_MCMC1) |
| 797 | #define bfin_write_SPT0_MCMC1(val) bfin_write16(SPT0_MCMC1, val) |
| 798 | #define pSPT0_MCMC2 ((uint16_t volatile *)SPT0_MCMC2) |
| 799 | #define bfin_read_SPT0_MCMC2() bfin_read16(SPT0_MCMC2) |
| 800 | #define bfin_write_SPT0_MCMC2(val) bfin_write16(SPT0_MCMC2, val) |
| 801 | #define pSPT0_CHNL ((uint16_t volatile *)SPT0_CHNL) |
| 802 | #define bfin_read_SPT0_CHNL() bfin_read16(SPT0_CHNL) |
| 803 | #define bfin_write_SPT0_CHNL(val) bfin_write16(SPT0_CHNL, val) |
| 804 | #define pSPT1_TX_CONFIG0 ((uint16_t volatile *)SPT1_TX_CONFIG0) |
| 805 | #define bfin_read_SPT1_TX_CONFIG0() bfin_read16(SPT1_TX_CONFIG0) |
| 806 | #define bfin_write_SPT1_TX_CONFIG0(val) bfin_write16(SPT1_TX_CONFIG0, val) |
| 807 | #define pSPT1_TX_CONFIG1 ((uint16_t volatile *)SPT1_TX_CONFIG1) |
| 808 | #define bfin_read_SPT1_TX_CONFIG1() bfin_read16(SPT1_TX_CONFIG1) |
| 809 | #define bfin_write_SPT1_TX_CONFIG1(val) bfin_write16(SPT1_TX_CONFIG1, val) |
| 810 | #define pSPT1_RX_CONFIG0 ((uint16_t volatile *)SPT1_RX_CONFIG0) |
| 811 | #define bfin_read_SPT1_RX_CONFIG0() bfin_read16(SPT1_RX_CONFIG0) |
| 812 | #define bfin_write_SPT1_RX_CONFIG0(val) bfin_write16(SPT1_RX_CONFIG0, val) |
| 813 | #define pSPT1_RX_CONFIG1 ((uint16_t volatile *)SPT1_RX_CONFIG1) |
| 814 | #define bfin_read_SPT1_RX_CONFIG1() bfin_read16(SPT1_RX_CONFIG1) |
| 815 | #define bfin_write_SPT1_RX_CONFIG1(val) bfin_write16(SPT1_RX_CONFIG1, val) |
| 816 | #define pSPT1_TX ((uint16_t volatile *)SPT1_TX) |
| 817 | #define bfin_read_SPT1_TX() bfin_read16(SPT1_TX) |
| 818 | #define bfin_write_SPT1_TX(val) bfin_write16(SPT1_TX, val) |
| 819 | #define pSPT1_RX ((uint16_t volatile *)SPT1_RX) |
| 820 | #define bfin_read_SPT1_RX() bfin_read16(SPT1_RX) |
| 821 | #define bfin_write_SPT1_RX(val) bfin_write16(SPT1_RX, val) |
| 822 | #define pSPT1_TSCLKDIV ((uint16_t volatile *)SPT1_TSCLKDIV) |
| 823 | #define bfin_read_SPT1_TSCLKDIV() bfin_read16(SPT1_TSCLKDIV) |
| 824 | #define bfin_write_SPT1_TSCLKDIV(val) bfin_write16(SPT1_TSCLKDIV, val) |
| 825 | #define pSPT1_RSCLKDIV ((uint16_t volatile *)SPT1_RSCLKDIV) |
| 826 | #define bfin_read_SPT1_RSCLKDIV() bfin_read16(SPT1_RSCLKDIV) |
| 827 | #define bfin_write_SPT1_RSCLKDIV(val) bfin_write16(SPT1_RSCLKDIV, val) |
| 828 | #define pSPT1_TFSDIV ((uint16_t volatile *)SPT1_TFSDIV) |
| 829 | #define bfin_read_SPT1_TFSDIV() bfin_read16(SPT1_TFSDIV) |
| 830 | #define bfin_write_SPT1_TFSDIV(val) bfin_write16(SPT1_TFSDIV, val) |
| 831 | #define pSPT1_RFSDIV ((uint16_t volatile *)SPT1_RFSDIV) |
| 832 | #define bfin_read_SPT1_RFSDIV() bfin_read16(SPT1_RFSDIV) |
| 833 | #define bfin_write_SPT1_RFSDIV(val) bfin_write16(SPT1_RFSDIV, val) |
| 834 | #define pSPT1_STAT ((uint16_t volatile *)SPT1_STAT) |
| 835 | #define bfin_read_SPT1_STAT() bfin_read16(SPT1_STAT) |
| 836 | #define bfin_write_SPT1_STAT(val) bfin_write16(SPT1_STAT, val) |
| 837 | #define pSPT1_MTCS0 ((uint32_t volatile *)SPT1_MTCS0) |
| 838 | #define bfin_read_SPT1_MTCS0() bfin_read32(SPT1_MTCS0) |
| 839 | #define bfin_write_SPT1_MTCS0(val) bfin_write32(SPT1_MTCS0, val) |
| 840 | #define pSPT1_MTCS1 ((uint32_t volatile *)SPT1_MTCS1) |
| 841 | #define bfin_read_SPT1_MTCS1() bfin_read32(SPT1_MTCS1) |
| 842 | #define bfin_write_SPT1_MTCS1(val) bfin_write32(SPT1_MTCS1, val) |
| 843 | #define pSPT1_MTCS2 ((uint32_t volatile *)SPT1_MTCS2) |
| 844 | #define bfin_read_SPT1_MTCS2() bfin_read32(SPT1_MTCS2) |
| 845 | #define bfin_write_SPT1_MTCS2(val) bfin_write32(SPT1_MTCS2, val) |
| 846 | #define pSPT1_MTCS3 ((uint32_t volatile *)SPT1_MTCS3) |
| 847 | #define bfin_read_SPT1_MTCS3() bfin_read32(SPT1_MTCS3) |
| 848 | #define bfin_write_SPT1_MTCS3(val) bfin_write32(SPT1_MTCS3, val) |
| 849 | #define pSPT1_MRCS0 ((uint32_t volatile *)SPT1_MRCS0) |
| 850 | #define bfin_read_SPT1_MRCS0() bfin_read32(SPT1_MRCS0) |
| 851 | #define bfin_write_SPT1_MRCS0(val) bfin_write32(SPT1_MRCS0, val) |
| 852 | #define pSPT1_MRCS1 ((uint32_t volatile *)SPT1_MRCS1) |
| 853 | #define bfin_read_SPT1_MRCS1() bfin_read32(SPT1_MRCS1) |
| 854 | #define bfin_write_SPT1_MRCS1(val) bfin_write32(SPT1_MRCS1, val) |
| 855 | #define pSPT1_MRCS2 ((uint32_t volatile *)SPT1_MRCS2) |
| 856 | #define bfin_read_SPT1_MRCS2() bfin_read32(SPT1_MRCS2) |
| 857 | #define bfin_write_SPT1_MRCS2(val) bfin_write32(SPT1_MRCS2, val) |
| 858 | #define pSPT1_MRCS3 ((uint32_t volatile *)SPT1_MRCS3) |
| 859 | #define bfin_read_SPT1_MRCS3() bfin_read32(SPT1_MRCS3) |
| 860 | #define bfin_write_SPT1_MRCS3(val) bfin_write32(SPT1_MRCS3, val) |
| 861 | #define pSPT1_MCMC1 ((uint16_t volatile *)SPT1_MCMC1) |
| 862 | #define bfin_read_SPT1_MCMC1() bfin_read16(SPT1_MCMC1) |
| 863 | #define bfin_write_SPT1_MCMC1(val) bfin_write16(SPT1_MCMC1, val) |
| 864 | #define pSPT1_MCMC2 ((uint16_t volatile *)SPT1_MCMC2) |
| 865 | #define bfin_read_SPT1_MCMC2() bfin_read16(SPT1_MCMC2) |
| 866 | #define bfin_write_SPT1_MCMC2(val) bfin_write16(SPT1_MCMC2, val) |
| 867 | #define pSPT1_CHNL ((uint16_t volatile *)SPT1_CHNL) |
| 868 | #define bfin_read_SPT1_CHNL() bfin_read16(SPT1_CHNL) |
| 869 | #define bfin_write_SPT1_CHNL(val) bfin_write16(SPT1_CHNL, val) |
| 870 | #define pPPI_CONTROL ((uint16_t volatile *)PPI_CONTROL) |
| 871 | #define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) |
| 872 | #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) |
| 873 | #define pPPI_STATUS ((uint16_t volatile *)PPI_STATUS) |
| 874 | #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) |
| 875 | #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) |
| 876 | #define pPPI_DELAY ((uint16_t volatile *)PPI_DELAY) |
| 877 | #define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) |
| 878 | #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) |
| 879 | #define pPPI_COUNT ((uint16_t volatile *)PPI_COUNT) |
| 880 | #define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) |
| 881 | #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) |
| 882 | #define pPPI_FRAME ((uint16_t volatile *)PPI_FRAME) |
| 883 | #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) |
| 884 | #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) |
| 885 | #define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control register (16-bit) */ |
| 886 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) |
| 887 | #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) |
| 888 | #define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register (16-bit) */ |
| 889 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) |
| 890 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) |
| 891 | #define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register (16-bit) */ |
| 892 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) |
| 893 | #define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) |
| 894 | #define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status register (16-bit) */ |
| 895 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) |
| 896 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) |
| 897 | #define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count register (16-bit) */ |
| 898 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) |
| 899 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) |
| Mike Frysinger | 621e579 | 2008-10-06 03:44:33 -0400 | [diff] [blame] | 900 | #define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register (16-bit) */ |
| 901 | #define bfin_read_SWRST() bfin_read16(SWRST) |
| 902 | #define bfin_write_SWRST(val) bfin_write16(SWRST, val) |
| Mike Frysinger | c6ea30e | 2009-02-18 12:51:48 -0500 | [diff] [blame] | 903 | #define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ |
| 904 | #define bfin_read_SYSCR() bfin_read16(SYSCR) |
| 905 | #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) |
| Mike Frysinger | d4d7730 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 906 | #define pEVT_OVERRIDE ((uint32_t volatile *)EVT_OVERRIDE) |
| 907 | #define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE) |
| 908 | #define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val) |
| Mike Frysinger | d4d7730 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 909 | #define pCHIPID ((uint32_t volatile *)CHIPID) |
| 910 | #define bfin_read_CHIPID() bfin_read32(CHIPID) |
| 911 | #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) |
| 912 | #define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ |
| 913 | #define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) |
| 914 | #define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) |
| 915 | #define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ |
| 916 | #define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) |
| 917 | #define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) |
| 918 | #define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ |
| 919 | #define bfin_read_TBUF() bfin_readPTR(TBUF) |
| 920 | #define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) |
| 921 | #define pPFCTL ((uint32_t volatile *)PFCTL) |
| 922 | #define bfin_read_PFCTL() bfin_read32(PFCTL) |
| 923 | #define bfin_write_PFCTL(val) bfin_write32(PFCTL, val) |
| 924 | #define pPFCNTR0 ((uint32_t volatile *)PFCNTR0) |
| 925 | #define bfin_read_PFCNTR0() bfin_read32(PFCNTR0) |
| 926 | #define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val) |
| 927 | #define pPFCNTR1 ((uint32_t volatile *)PFCNTR1) |
| 928 | #define bfin_read_PFCNTR1() bfin_read32(PFCNTR1) |
| 929 | #define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val) |
| 930 | #define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */ |
| 931 | #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) |
| 932 | #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) |
| 933 | #define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */ |
| 934 | #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) |
| 935 | #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) |
| 936 | #define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */ |
| 937 | #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) |
| 938 | #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) |
| 939 | #define pRTC_STAT ((uint32_t volatile *)RTC_STAT) |
| 940 | #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) |
| 941 | #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) |
| 942 | #define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) |
| 943 | #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) |
| 944 | #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) |
| 945 | #define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) |
| 946 | #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) |
| 947 | #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) |
| 948 | #define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) |
| 949 | #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) |
| 950 | #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) |
| 951 | #define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) |
| 952 | #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) |
| 953 | #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) |
| 954 | #define pRTC_PREN ((uint16_t volatile *)RTC_PREN) |
| 955 | #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) |
| 956 | #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) |
| 957 | #define pSPI_CTL ((uint16_t volatile *)SPI_CTL) |
| 958 | #define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) |
| 959 | #define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) |
| 960 | #define pSPI_FLG ((uint16_t volatile *)SPI_FLG) |
| 961 | #define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) |
| 962 | #define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) |
| 963 | #define pSPI_STAT ((uint16_t volatile *)SPI_STAT) |
| 964 | #define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) |
| 965 | #define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) |
| 966 | #define pSPI_TDBR ((uint16_t volatile *)SPI_TDBR) |
| 967 | #define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) |
| 968 | #define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) |
| 969 | #define pSPI_RDBR ((uint16_t volatile *)SPI_RDBR) |
| 970 | #define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) |
| 971 | #define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) |
| 972 | #define pSPI_BAUD ((uint16_t volatile *)SPI_BAUD) |
| 973 | #define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) |
| 974 | #define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) |
| 975 | #define pSPI_SHADOW ((uint16_t volatile *)SPI_SHADOW) |
| 976 | #define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) |
| 977 | #define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) |
| 978 | #define pFIO_FLAG_D ((uint16_t volatile *)FIO_FLAG_D) |
| 979 | #define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) |
| 980 | #define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val) |
| 981 | #define pFIO_FLAG_C ((uint16_t volatile *)FIO_FLAG_C) |
| 982 | #define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) |
| 983 | #define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val) |
| 984 | #define pFIO_FLAG_S ((uint16_t volatile *)FIO_FLAG_S) |
| 985 | #define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) |
| 986 | #define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val) |
| 987 | #define pFIO_FLAG_T ((uint16_t volatile *)FIO_FLAG_T) |
| 988 | #define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) |
| 989 | #define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val) |
| 990 | #define pFIO_MASKA_D ((uint16_t volatile *)FIO_MASKA_D) |
| 991 | #define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D) |
| 992 | #define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D, val) |
| 993 | #define pFIO_MASKA_C ((uint16_t volatile *)FIO_MASKA_C) |
| 994 | #define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C) |
| 995 | #define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C, val) |
| 996 | #define pFIO_MASKA_S ((uint16_t volatile *)FIO_MASKA_S) |
| 997 | #define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S) |
| 998 | #define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S, val) |
| 999 | #define pFIO_MASKA_T ((uint16_t volatile *)FIO_MASKA_T) |
| 1000 | #define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T) |
| 1001 | #define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T, val) |
| 1002 | #define pFIO_MASKB_D ((uint16_t volatile *)FIO_MASKB_D) |
| 1003 | #define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D) |
| 1004 | #define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D, val) |
| 1005 | #define pFIO_MASKB_C ((uint16_t volatile *)FIO_MASKB_C) |
| 1006 | #define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C) |
| 1007 | #define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C, val) |
| 1008 | #define pFIO_MASKB_S ((uint16_t volatile *)FIO_MASKB_S) |
| 1009 | #define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S) |
| 1010 | #define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S, val) |
| 1011 | #define pFIO_MASKB_T ((uint16_t volatile *)FIO_MASKB_T) |
| 1012 | #define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) |
| 1013 | #define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T, val) |
| 1014 | #define pFIO_DIR ((uint16_t volatile *)FIO_DIR) |
| 1015 | #define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) |
| 1016 | #define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR, val) |
| 1017 | #define pFIO_POLAR ((uint16_t volatile *)FIO_POLAR) |
| 1018 | #define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR) |
| 1019 | #define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR, val) |
| 1020 | #define pFIO_EDGE ((uint16_t volatile *)FIO_EDGE) |
| 1021 | #define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE) |
| 1022 | #define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE, val) |
| 1023 | #define pFIO_BOTH ((uint16_t volatile *)FIO_BOTH) |
| 1024 | #define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH) |
| 1025 | #define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH, val) |
| 1026 | #define pFIO_INEN ((uint16_t volatile *)FIO_INEN) |
| 1027 | #define bfin_read_FIO_INEN() bfin_read16(FIO_INEN) |
| 1028 | #define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN, val) |
| 1029 | #define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */ |
| 1030 | #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) |
| 1031 | #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) |
| 1032 | #define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */ |
| 1033 | #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) |
| 1034 | #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) |
| 1035 | #define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */ |
| 1036 | #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) |
| 1037 | #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) |
| 1038 | #define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */ |
| 1039 | #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) |
| 1040 | #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) |
| 1041 | #define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */ |
| 1042 | #define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) |
| 1043 | #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) |
| 1044 | #define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */ |
| 1045 | #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) |
| 1046 | #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) |
| 1047 | #define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */ |
| 1048 | #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) |
| 1049 | #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) |
| 1050 | #define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */ |
| 1051 | #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) |
| 1052 | #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) |
| 1053 | #define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */ |
| 1054 | #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) |
| 1055 | #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) |
| 1056 | #define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */ |
| 1057 | #define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) |
| 1058 | #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) |
| 1059 | #define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */ |
| 1060 | #define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) |
| 1061 | #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) |
| 1062 | #define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */ |
| 1063 | #define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) |
| 1064 | #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) |
| 1065 | #define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */ |
| 1066 | #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) |
| 1067 | #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) |
| 1068 | #define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */ |
| 1069 | #define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) |
| 1070 | #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) |
| 1071 | #define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */ |
| 1072 | #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) |
| 1073 | #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) |
| 1074 | #define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */ |
| 1075 | #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) |
| 1076 | #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) |
| 1077 | #define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */ |
| 1078 | #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) |
| 1079 | #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) |
| 1080 | #define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */ |
| 1081 | #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) |
| 1082 | #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) |
| 1083 | #define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */ |
| 1084 | #define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) |
| 1085 | #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) |
| 1086 | #define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */ |
| 1087 | #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) |
| 1088 | #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) |
| 1089 | #define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */ |
| 1090 | #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) |
| 1091 | #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) |
| 1092 | #define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */ |
| 1093 | #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) |
| 1094 | #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) |
| 1095 | #define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */ |
| 1096 | #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) |
| 1097 | #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) |
| 1098 | #define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */ |
| 1099 | #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) |
| 1100 | #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) |
| 1101 | #define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */ |
| 1102 | #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) |
| 1103 | #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) |
| 1104 | #define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */ |
| 1105 | #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) |
| 1106 | #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) |
| 1107 | #define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */ |
| 1108 | #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) |
| 1109 | #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) |
| 1110 | #define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */ |
| 1111 | #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) |
| 1112 | #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) |
| 1113 | #define pDMA0_NEXT_DESC_PTR ((uint32_t volatile *)DMA0_NEXT_DESC_PTR) |
| 1114 | #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) |
| 1115 | #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) |
| 1116 | #define pDMA0_START_ADDR ((uint32_t volatile *)DMA0_START_ADDR) |
| 1117 | #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) |
| 1118 | #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) |
| 1119 | #define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */ |
| 1120 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) |
| 1121 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) |
| 1122 | #define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) |
| 1123 | #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) |
| 1124 | #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) |
| 1125 | #define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) |
| 1126 | #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) |
| 1127 | #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) |
| 1128 | #define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) |
| 1129 | #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) |
| 1130 | #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) |
| 1131 | #define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) |
| 1132 | #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) |
| 1133 | #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) |
| 1134 | #define pDMA0_CURR_DESC_PTR ((uint32_t volatile *)DMA0_CURR_DESC_PTR) |
| 1135 | #define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) |
| 1136 | #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) |
| 1137 | #define pDMA0_CURR_ADDR ((uint32_t volatile *)DMA0_CURR_ADDR) |
| 1138 | #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) |
| 1139 | #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) |
| 1140 | #define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) |
| 1141 | #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) |
| 1142 | #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) |
| 1143 | #define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) |
| 1144 | #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) |
| 1145 | #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) |
| 1146 | #define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) |
| 1147 | #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) |
| 1148 | #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) |
| 1149 | #define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) |
| 1150 | #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) |
| 1151 | #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) |
| 1152 | #define pDMA1_NEXT_DESC_PTR ((uint32_t volatile *)DMA1_NEXT_DESC_PTR) |
| 1153 | #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) |
| 1154 | #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) |
| 1155 | #define pDMA1_START_ADDR ((uint32_t volatile *)DMA1_START_ADDR) |
| 1156 | #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) |
| 1157 | #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) |
| 1158 | #define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */ |
| 1159 | #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) |
| 1160 | #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) |
| 1161 | #define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) |
| 1162 | #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) |
| 1163 | #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) |
| 1164 | #define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) |
| 1165 | #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) |
| 1166 | #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) |
| 1167 | #define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) |
| 1168 | #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) |
| 1169 | #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) |
| 1170 | #define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) |
| 1171 | #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) |
| 1172 | #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) |
| 1173 | #define pDMA1_CURR_DESC_PTR ((uint32_t volatile *)DMA1_CURR_DESC_PTR) |
| 1174 | #define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) |
| 1175 | #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) |
| 1176 | #define pDMA1_CURR_ADDR ((uint32_t volatile *)DMA1_CURR_ADDR) |
| 1177 | #define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) |
| 1178 | #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) |
| 1179 | #define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) |
| 1180 | #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) |
| 1181 | #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) |
| 1182 | #define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) |
| 1183 | #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) |
| 1184 | #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) |
| 1185 | #define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) |
| 1186 | #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) |
| 1187 | #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) |
| 1188 | #define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) |
| 1189 | #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) |
| 1190 | #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) |
| 1191 | #define pDMA2_NEXT_DESC_PTR ((uint32_t volatile *)DMA2_NEXT_DESC_PTR) |
| 1192 | #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) |
| 1193 | #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) |
| 1194 | #define pDMA2_START_ADDR ((uint32_t volatile *)DMA2_START_ADDR) |
| 1195 | #define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) |
| 1196 | #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) |
| 1197 | #define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */ |
| 1198 | #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) |
| 1199 | #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) |
| 1200 | #define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) |
| 1201 | #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) |
| 1202 | #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) |
| 1203 | #define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) |
| 1204 | #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) |
| 1205 | #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) |
| 1206 | #define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) |
| 1207 | #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) |
| 1208 | #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) |
| 1209 | #define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) |
| 1210 | #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) |
| 1211 | #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) |
| 1212 | #define pDMA2_CURR_DESC_PTR ((uint32_t volatile *)DMA2_CURR_DESC_PTR) |
| 1213 | #define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) |
| 1214 | #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) |
| 1215 | #define pDMA2_CURR_ADDR ((uint32_t volatile *)DMA2_CURR_ADDR) |
| 1216 | #define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) |
| 1217 | #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) |
| 1218 | #define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) |
| 1219 | #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) |
| 1220 | #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) |
| 1221 | #define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) |
| 1222 | #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) |
| 1223 | #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) |
| 1224 | #define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) |
| 1225 | #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) |
| 1226 | #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) |
| 1227 | #define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) |
| 1228 | #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) |
| 1229 | #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) |
| 1230 | #define pDMA3_NEXT_DESC_PTR ((uint32_t volatile *)DMA3_NEXT_DESC_PTR) |
| 1231 | #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) |
| 1232 | #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) |
| 1233 | #define pDMA3_START_ADDR ((uint32_t volatile *)DMA3_START_ADDR) |
| 1234 | #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) |
| 1235 | #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) |
| 1236 | #define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */ |
| 1237 | #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) |
| 1238 | #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) |
| 1239 | #define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) |
| 1240 | #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) |
| 1241 | #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) |
| 1242 | #define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) |
| 1243 | #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) |
| 1244 | #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) |
| 1245 | #define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) |
| 1246 | #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) |
| 1247 | #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) |
| 1248 | #define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) |
| 1249 | #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) |
| 1250 | #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) |
| 1251 | #define pDMA3_CURR_DESC_PTR ((uint32_t volatile *)DMA3_CURR_DESC_PTR) |
| 1252 | #define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) |
| 1253 | #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) |
| 1254 | #define pDMA3_CURR_ADDR ((uint32_t volatile *)DMA3_CURR_ADDR) |
| 1255 | #define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) |
| 1256 | #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) |
| 1257 | #define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) |
| 1258 | #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) |
| 1259 | #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) |
| 1260 | #define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) |
| 1261 | #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) |
| 1262 | #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) |
| 1263 | #define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) |
| 1264 | #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) |
| 1265 | #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) |
| 1266 | #define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) |
| 1267 | #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) |
| 1268 | #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) |
| 1269 | #define pDMA4_NEXT_DESC_PTR ((uint32_t volatile *)DMA4_NEXT_DESC_PTR) |
| 1270 | #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) |
| 1271 | #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) |
| 1272 | #define pDMA4_START_ADDR ((uint32_t volatile *)DMA4_START_ADDR) |
| 1273 | #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) |
| 1274 | #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) |
| 1275 | #define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */ |
| 1276 | #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) |
| 1277 | #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) |
| 1278 | #define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) |
| 1279 | #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) |
| 1280 | #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) |
| 1281 | #define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) |
| 1282 | #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) |
| 1283 | #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) |
| 1284 | #define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) |
| 1285 | #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) |
| 1286 | #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) |
| 1287 | #define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) |
| 1288 | #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) |
| 1289 | #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) |
| 1290 | #define pDMA4_CURR_DESC_PTR ((uint32_t volatile *)DMA4_CURR_DESC_PTR) |
| 1291 | #define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) |
| 1292 | #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) |
| 1293 | #define pDMA4_CURR_ADDR ((uint32_t volatile *)DMA4_CURR_ADDR) |
| 1294 | #define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) |
| 1295 | #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) |
| 1296 | #define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) |
| 1297 | #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) |
| 1298 | #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) |
| 1299 | #define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) |
| 1300 | #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) |
| 1301 | #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) |
| 1302 | #define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) |
| 1303 | #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) |
| 1304 | #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) |
| 1305 | #define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) |
| 1306 | #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) |
| 1307 | #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) |
| 1308 | #define pDMA5_NEXT_DESC_PTR ((uint32_t volatile *)DMA5_NEXT_DESC_PTR) |
| 1309 | #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) |
| 1310 | #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) |
| 1311 | #define pDMA5_START_ADDR ((uint32_t volatile *)DMA5_START_ADDR) |
| 1312 | #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) |
| 1313 | #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) |
| 1314 | #define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */ |
| 1315 | #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) |
| 1316 | #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) |
| 1317 | #define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) |
| 1318 | #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) |
| 1319 | #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) |
| 1320 | #define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) |
| 1321 | #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) |
| 1322 | #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) |
| 1323 | #define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) |
| 1324 | #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) |
| 1325 | #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) |
| 1326 | #define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) |
| 1327 | #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) |
| 1328 | #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) |
| 1329 | #define pDMA5_CURR_DESC_PTR ((uint32_t volatile *)DMA5_CURR_DESC_PTR) |
| 1330 | #define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) |
| 1331 | #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) |
| 1332 | #define pDMA5_CURR_ADDR ((uint32_t volatile *)DMA5_CURR_ADDR) |
| 1333 | #define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) |
| 1334 | #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) |
| 1335 | #define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) |
| 1336 | #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) |
| 1337 | #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) |
| 1338 | #define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) |
| 1339 | #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) |
| 1340 | #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) |
| 1341 | #define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) |
| 1342 | #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) |
| 1343 | #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) |
| 1344 | #define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) |
| 1345 | #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) |
| 1346 | #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) |
| 1347 | #define pDMA6_NEXT_DESC_PTR ((uint32_t volatile *)DMA6_NEXT_DESC_PTR) |
| 1348 | #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) |
| 1349 | #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) |
| 1350 | #define pDMA6_START_ADDR ((uint32_t volatile *)DMA6_START_ADDR) |
| 1351 | #define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) |
| 1352 | #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) |
| 1353 | #define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */ |
| 1354 | #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) |
| 1355 | #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) |
| 1356 | #define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) |
| 1357 | #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) |
| 1358 | #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) |
| 1359 | #define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) |
| 1360 | #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) |
| 1361 | #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) |
| 1362 | #define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) |
| 1363 | #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) |
| 1364 | #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) |
| 1365 | #define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) |
| 1366 | #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) |
| 1367 | #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) |
| 1368 | #define pDMA6_CURR_DESC_PTR ((uint32_t volatile *)DMA6_CURR_DESC_PTR) |
| 1369 | #define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) |
| 1370 | #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) |
| 1371 | #define pDMA6_CURR_ADDR ((uint32_t volatile *)DMA6_CURR_ADDR) |
| 1372 | #define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) |
| 1373 | #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) |
| 1374 | #define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) |
| 1375 | #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) |
| 1376 | #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) |
| 1377 | #define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) |
| 1378 | #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) |
| 1379 | #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) |
| 1380 | #define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) |
| 1381 | #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) |
| 1382 | #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) |
| 1383 | #define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) |
| 1384 | #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) |
| 1385 | #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) |
| 1386 | #define pDMA7_NEXT_DESC_PTR ((uint32_t volatile *)DMA7_NEXT_DESC_PTR) |
| 1387 | #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) |
| 1388 | #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) |
| 1389 | #define pDMA7_START_ADDR ((uint32_t volatile *)DMA7_START_ADDR) |
| 1390 | #define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) |
| 1391 | #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) |
| 1392 | #define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */ |
| 1393 | #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) |
| 1394 | #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) |
| 1395 | #define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) |
| 1396 | #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) |
| 1397 | #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) |
| 1398 | #define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) |
| 1399 | #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) |
| 1400 | #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) |
| 1401 | #define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) |
| 1402 | #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) |
| 1403 | #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) |
| 1404 | #define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) |
| 1405 | #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) |
| 1406 | #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) |
| 1407 | #define pDMA7_CURR_DESC_PTR ((uint32_t volatile *)DMA7_CURR_DESC_PTR) |
| 1408 | #define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) |
| 1409 | #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) |
| 1410 | #define pDMA7_CURR_ADDR ((uint32_t volatile *)DMA7_CURR_ADDR) |
| 1411 | #define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) |
| 1412 | #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) |
| 1413 | #define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) |
| 1414 | #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) |
| 1415 | #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) |
| 1416 | #define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) |
| 1417 | #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) |
| 1418 | #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) |
| 1419 | #define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) |
| 1420 | #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) |
| 1421 | #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) |
| 1422 | #define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) |
| 1423 | #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) |
| 1424 | #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) |
| 1425 | #define pMDMA_D0_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_D0_NEXT_DESC_PTR) |
| 1426 | #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) |
| 1427 | #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) |
| 1428 | #define pMDMA_D0_START_ADDR ((uint32_t volatile *)MDMA_D0_START_ADDR) |
| 1429 | #define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) |
| 1430 | #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) |
| 1431 | #define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) |
| 1432 | #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) |
| 1433 | #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) |
| 1434 | #define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) |
| 1435 | #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) |
| 1436 | #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) |
| 1437 | #define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) |
| 1438 | #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) |
| 1439 | #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) |
| 1440 | #define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) |
| 1441 | #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) |
| 1442 | #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) |
| 1443 | #define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) |
| 1444 | #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) |
| 1445 | #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) |
| 1446 | #define pMDMA_D0_CURR_DESC_PTR ((uint32_t volatile *)MDMA_D0_CURR_DESC_PTR) |
| 1447 | #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) |
| 1448 | #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) |
| 1449 | #define pMDMA_D0_CURR_ADDR ((uint32_t volatile *)MDMA_D0_CURR_ADDR) |
| 1450 | #define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) |
| 1451 | #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) |
| 1452 | #define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) |
| 1453 | #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) |
| 1454 | #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) |
| 1455 | #define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) |
| 1456 | #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) |
| 1457 | #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) |
| 1458 | #define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) |
| 1459 | #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) |
| 1460 | #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) |
| 1461 | #define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) |
| 1462 | #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) |
| 1463 | #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) |
| 1464 | #define pMDMA_S0_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_S0_NEXT_DESC_PTR) |
| 1465 | #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) |
| 1466 | #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) |
| 1467 | #define pMDMA_S0_START_ADDR ((uint32_t volatile *)MDMA_S0_START_ADDR) |
| 1468 | #define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) |
| 1469 | #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) |
| 1470 | #define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) |
| 1471 | #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) |
| 1472 | #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) |
| 1473 | #define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) |
| 1474 | #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) |
| 1475 | #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) |
| 1476 | #define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) |
| 1477 | #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) |
| 1478 | #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) |
| 1479 | #define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) |
| 1480 | #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) |
| 1481 | #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) |
| 1482 | #define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) |
| 1483 | #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) |
| 1484 | #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) |
| 1485 | #define pMDMA_S0_CURR_DESC_PTR ((uint32_t volatile *)MDMA_S0_CURR_DESC_PTR) |
| 1486 | #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) |
| 1487 | #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) |
| 1488 | #define pMDMA_S0_CURR_ADDR ((uint32_t volatile *)MDMA_S0_CURR_ADDR) |
| 1489 | #define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) |
| 1490 | #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) |
| 1491 | #define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) |
| 1492 | #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) |
| 1493 | #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) |
| 1494 | #define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) |
| 1495 | #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) |
| 1496 | #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) |
| 1497 | #define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) |
| 1498 | #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) |
| 1499 | #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) |
| 1500 | #define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) |
| 1501 | #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) |
| 1502 | #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) |
| 1503 | #define pMDMA_D1_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_D1_NEXT_DESC_PTR) |
| 1504 | #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) |
| 1505 | #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) |
| 1506 | #define pMDMA_D1_START_ADDR ((uint32_t volatile *)MDMA_D1_START_ADDR) |
| 1507 | #define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) |
| 1508 | #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) |
| 1509 | #define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */ |
| 1510 | #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) |
| 1511 | #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) |
| 1512 | #define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) |
| 1513 | #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) |
| 1514 | #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) |
| 1515 | #define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) |
| 1516 | #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) |
| 1517 | #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) |
| 1518 | #define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) |
| 1519 | #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) |
| 1520 | #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) |
| 1521 | #define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) |
| 1522 | #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) |
| 1523 | #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) |
| 1524 | #define pMDMA_D1_CURR_DESC_PTR ((uint32_t volatile *)MDMA_D1_CURR_DESC_PTR) |
| 1525 | #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) |
| 1526 | #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) |
| 1527 | #define pMDMA_D1_CURR_ADDR ((uint32_t volatile *)MDMA_D1_CURR_ADDR) |
| 1528 | #define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) |
| 1529 | #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) |
| 1530 | #define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) |
| 1531 | #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) |
| 1532 | #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) |
| 1533 | #define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) |
| 1534 | #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) |
| 1535 | #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) |
| 1536 | #define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) |
| 1537 | #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) |
| 1538 | #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) |
| 1539 | #define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) |
| 1540 | #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) |
| 1541 | #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) |
| 1542 | #define pMDMA_S1_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_S1_NEXT_DESC_PTR) |
| 1543 | #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) |
| 1544 | #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) |
| 1545 | #define pMDMA_S1_START_ADDR ((uint32_t volatile *)MDMA_S1_START_ADDR) |
| 1546 | #define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) |
| 1547 | #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) |
| 1548 | #define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) |
| 1549 | #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) |
| 1550 | #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) |
| 1551 | #define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) |
| 1552 | #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) |
| 1553 | #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) |
| 1554 | #define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) |
| 1555 | #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) |
| 1556 | #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) |
| 1557 | #define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) |
| 1558 | #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) |
| 1559 | #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) |
| 1560 | #define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) |
| 1561 | #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) |
| 1562 | #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) |
| 1563 | #define pMDMA_S1_CURR_DESC_PTR ((uint32_t volatile *)MDMA_S1_CURR_DESC_PTR) |
| 1564 | #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) |
| 1565 | #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) |
| 1566 | #define pMDMA_S1_CURR_ADDR ((uint32_t volatile *)MDMA_S1_CURR_ADDR) |
| 1567 | #define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) |
| 1568 | #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) |
| 1569 | #define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) |
| 1570 | #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) |
| 1571 | #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) |
| 1572 | #define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) |
| 1573 | #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) |
| 1574 | #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) |
| 1575 | #define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) |
| 1576 | #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) |
| 1577 | #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) |
| 1578 | #define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) |
| 1579 | #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) |
| 1580 | #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) |
| 1581 | #define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) |
| 1582 | #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) |
| 1583 | #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) |
| 1584 | #define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) |
| 1585 | #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) |
| 1586 | #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) |
| 1587 | #define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) |
| 1588 | #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) |
| 1589 | #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) |
| 1590 | #define pEBIU_SDGCTL ((uint32_t volatile *)EBIU_SDGCTL) |
| 1591 | #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) |
| 1592 | #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) |
| 1593 | #define pEBIU_SDBCTL ((uint16_t volatile *)EBIU_SDBCTL) |
| 1594 | #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) |
| 1595 | #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) |
| 1596 | #define pEBIU_SDRRC ((uint16_t volatile *)EBIU_SDRRC) |
| 1597 | #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) |
| 1598 | #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) |
| 1599 | #define pEBIU_SDSTAT ((uint16_t volatile *)EBIU_SDSTAT) |
| 1600 | #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) |
| 1601 | #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) |
| 1602 | #define pDMA_TC_CNT ((uint16_t volatile *)DMA_TC_CNT) |
| 1603 | #define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) |
| 1604 | #define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) |
| 1605 | #define pDMA_TC_PER ((uint16_t volatile *)DMA_TC_PER) |
| 1606 | #define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) |
| 1607 | #define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) |
| 1608 | |
| 1609 | #endif /* __BFIN_CDEF_ADSP_EDN_extended__ */ |