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Fabio Estevam7dd65452012-09-24 08:09:33 +00001/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
Otavio Salvador903e7792012-10-02 09:22:10 +00004 * Configuration settings for the Freescale i.MX6Q SabreAuto board.
Fabio Estevam7dd65452012-09-24 08:09:33 +00005 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Fabio Estevam7dd65452012-09-24 08:09:33 +00007 */
8
9#ifndef __MX6QSABREAUTO_CONFIG_H
10#define __MX6QSABREAUTO_CONFIG_H
Fabio Estevam7dd65452012-09-24 08:09:33 +000011
12#define CONFIG_MACH_TYPE 3529
13#define CONFIG_MXC_UART_BASE UART4_BASE
Otavio Salvador51535d92012-09-26 11:37:01 +000014#define CONFIG_CONSOLE_DEV "ttymxc3"
Otavio Salvador903e7792012-10-02 09:22:10 +000015#define CONFIG_MMCROOT "/dev/mmcblk0p2"
Fabio Estevam7dd65452012-09-24 08:09:33 +000016#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
17
Knut Wohlrab73448b12013-01-21 23:11:21 +000018/* USB Configs */
Knut Wohlrab73448b12013-01-21 23:11:21 +000019#define CONFIG_USB_EHCI
20#define CONFIG_USB_EHCI_MX6
21#define CONFIG_USB_STORAGE
22#define CONFIG_USB_HOST_ETHER
23#define CONFIG_USB_ETHER_ASIX
Troy Kiskyd1a52862013-10-10 15:27:59 -070024#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
25#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
Knut Wohlrab73448b12013-01-21 23:11:21 +000026#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
27#define CONFIG_MXC_USB_FLAGS 0
28
Ye.Li8fe280f2014-10-30 18:53:49 +080029#define CONFIG_PCA953X
30#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
31
Pierre Aubertc1747972013-06-04 09:00:15 +020032#include "mx6sabre_common.h"
Otavio Salvador51535d92012-09-26 11:37:01 +000033
Fabio Estevamcdbdde32014-11-14 11:27:23 -020034#undef CONFIG_SYS_NO_FLASH
35#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
36#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
37#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
38#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
39#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
40#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
41#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
42#define CONFIG_SYS_FLASH_EMPTY_INFO
43
Shawn Guode7d02a2012-12-30 14:14:59 +000044#define CONFIG_SYS_FSL_USDHC_NUM 2
45#if defined(CONFIG_ENV_IS_IN_MMC)
46#define CONFIG_SYS_MMC_ENV_DEV 0
47#endif
48
Renato Frias19578162013-05-13 18:01:12 +000049/* I2C Configs */
tremb089d032013-09-21 18:13:36 +020050#define CONFIG_SYS_I2C
51#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)03544c62015-09-21 22:43:38 +020052#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
53#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf8cb1012015-03-20 10:20:40 -070054#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Renato Frias19578162013-05-13 18:01:12 +000055#define CONFIG_SYS_I2C_SPEED 100000
56
Ye.Li83bb3212014-11-12 14:02:05 +080057/* NAND flash command */
58#define CONFIG_CMD_NAND
59#define CONFIG_CMD_NAND_TRIMFFS
60
61/* NAND stuff */
62#define CONFIG_NAND_MXS
63#define CONFIG_SYS_MAX_NAND_DEVICE 1
64#define CONFIG_SYS_NAND_BASE 0x40000000
65#define CONFIG_SYS_NAND_5_ADDR_CYCLE
66#define CONFIG_SYS_NAND_ONFI_DETECTION
67
68/* DMA stuff, needed for GPMI/MXS NAND support */
69#define CONFIG_APBH_DMA
70#define CONFIG_APBH_DMA_BURST
71#define CONFIG_APBH_DMA_BURST8
72
Ye.Li593243d2014-11-06 16:29:02 +080073/* PMIC */
74#define CONFIG_POWER
75#define CONFIG_POWER_I2C
76#define CONFIG_POWER_PFUZE100
77#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
78
Fabio Estevam7dd65452012-09-24 08:09:33 +000079#endif /* __MX6QSABREAUTO_CONFIG_H */