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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass91785f72015-01-27 22:13:39 -07002/*
3 * Copyright (C) 2015, Google, Inc
4 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
Simon Glass91785f72015-01-27 22:13:39 -07005 */
6
7#include <common.h>
Simon Glassb7c6bae2017-07-30 19:24:01 -07008#include <dm.h>
Simon Glass91785f72015-01-27 22:13:39 -07009#include <errno.h>
Simon Glassdba7ee42020-07-07 21:32:12 -060010#include <log.h>
Simon Glass91785f72015-01-27 22:13:39 -070011#include <malloc.h>
Simon Glassb7c6bae2017-07-30 19:24:01 -070012#include <mapmem.h>
Simon Glass8a8a8312021-01-13 20:29:54 -070013#include <mmc.h>
Simon Glass91785f72015-01-27 22:13:39 -070014#include <sdhci.h>
Simon Glassdba7ee42020-07-07 21:32:12 -060015#include <acpi/acpigen.h>
16#include <acpi/acpi_device.h>
17#include <acpi/acpi_dp.h>
18#include <asm-generic/gpio.h>
19#include <dm/acpi.h>
Simon Glass91785f72015-01-27 22:13:39 -070020
Simon Glass60868632021-01-13 20:29:52 -070021/* Type of MMC device */
22enum {
23 TYPE_SD,
24 TYPE_EMMC,
25};
26
Simon Glassb7c6bae2017-07-30 19:24:01 -070027struct pci_mmc_plat {
28 struct mmc_config cfg;
29 struct mmc mmc;
30};
31
32struct pci_mmc_priv {
33 struct sdhci_host host;
34 void *base;
Simon Glassdba7ee42020-07-07 21:32:12 -060035 struct gpio_desc cd_gpio;
Simon Glassb7c6bae2017-07-30 19:24:01 -070036};
37
38static int pci_mmc_probe(struct udevice *dev)
Simon Glass91785f72015-01-27 22:13:39 -070039{
Simon Glassb7c6bae2017-07-30 19:24:01 -070040 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
Simon Glassc69cda22020-12-03 16:55:20 -070041 struct pci_mmc_plat *plat = dev_get_plat(dev);
Simon Glassb7c6bae2017-07-30 19:24:01 -070042 struct pci_mmc_priv *priv = dev_get_priv(dev);
43 struct sdhci_host *host = &priv->host;
Simon Glass8a8a8312021-01-13 20:29:54 -070044 struct blk_desc *desc;
Simon Glass91785f72015-01-27 22:13:39 -070045 int ret;
Simon Glass91785f72015-01-27 22:13:39 -070046
Simon Glass8a8a8312021-01-13 20:29:54 -070047 ret = mmc_of_parse(dev, &plat->cfg);
48 if (ret)
49 return ret;
50 desc = mmc_get_blk_desc(&plat->mmc);
51 desc->removable = !(plat->cfg.host_caps & MMC_CAP_NONREMOVABLE);
52
Bernhard Messerklinger0851f342018-02-15 09:09:43 +010053 host->ioaddr = (void *)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0,
54 PCI_REGION_MEM);
Simon Glassb7c6bae2017-07-30 19:24:01 -070055 host->name = dev->name;
Simon Glass326aae22021-03-15 18:00:08 +130056 host->cd_gpio = priv->cd_gpio;
Peng Fana5abe152019-08-06 02:47:56 +000057 host->mmc = &plat->mmc;
58 host->mmc->dev = dev;
Simon Glassb7c6bae2017-07-30 19:24:01 -070059 ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
60 if (ret)
61 return ret;
Simon Glassb7c6bae2017-07-30 19:24:01 -070062 host->mmc->priv = &priv->host;
Simon Glassb7c6bae2017-07-30 19:24:01 -070063 upriv->mmc = host->mmc;
Simon Glass91785f72015-01-27 22:13:39 -070064
Simon Glassb7c6bae2017-07-30 19:24:01 -070065 return sdhci_probe(dev);
Simon Glass91785f72015-01-27 22:13:39 -070066}
Simon Glassb7c6bae2017-07-30 19:24:01 -070067
Simon Glassd1998a92020-12-03 16:55:21 -070068static int pci_mmc_of_to_plat(struct udevice *dev)
Simon Glassdba7ee42020-07-07 21:32:12 -060069{
Harm Berntsen7b4fe6d2020-11-06 12:20:44 +000070 if (CONFIG_IS_ENABLED(DM_GPIO)) {
71 struct pci_mmc_priv *priv = dev_get_priv(dev);
Simon Glass326aae22021-03-15 18:00:08 +130072 int ret;
Simon Glassdba7ee42020-07-07 21:32:12 -060073
Simon Glass326aae22021-03-15 18:00:08 +130074 ret = gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
75 GPIOD_IS_IN);
76 log_debug("cd-gpio %s done, ret=%d\n", dev->name, ret);
Harm Berntsen7b4fe6d2020-11-06 12:20:44 +000077 }
Simon Glassdba7ee42020-07-07 21:32:12 -060078
79 return 0;
80}
81
Simon Glassb7c6bae2017-07-30 19:24:01 -070082static int pci_mmc_bind(struct udevice *dev)
83{
Simon Glassc69cda22020-12-03 16:55:20 -070084 struct pci_mmc_plat *plat = dev_get_plat(dev);
Simon Glassb7c6bae2017-07-30 19:24:01 -070085
86 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
87}
88
Simon Glassdba7ee42020-07-07 21:32:12 -060089static int pci_mmc_acpi_fill_ssdt(const struct udevice *dev,
90 struct acpi_ctx *ctx)
91{
92 struct pci_mmc_priv *priv = dev_get_priv(dev);
93 char path[ACPI_PATH_MAX];
94 struct acpi_gpio gpio;
95 struct acpi_dp *dp;
96 int ret;
97
Simon Glass7d14ee42020-12-19 10:40:13 -070098 if (!dev_has_ofnode(dev))
Simon Glassdba7ee42020-07-07 21:32:12 -060099 return 0;
Simon Glass60868632021-01-13 20:29:52 -0700100 if (dev_get_driver_data(dev) == TYPE_EMMC)
101 return 0;
Simon Glassdba7ee42020-07-07 21:32:12 -0600102
103 ret = gpio_get_acpi(&priv->cd_gpio, &gpio);
104 if (ret)
105 return log_msg_ret("gpio", ret);
106 gpio.type = ACPI_GPIO_TYPE_INTERRUPT;
107 gpio.pull = ACPI_GPIO_PULL_NONE;
108 gpio.irq.mode = ACPI_IRQ_EDGE_TRIGGERED;
109 gpio.irq.polarity = ACPI_IRQ_ACTIVE_BOTH;
110 gpio.irq.shared = ACPI_IRQ_SHARED;
111 gpio.irq.wake = ACPI_IRQ_WAKE;
112 gpio.interrupt_debounce_timeout = 10000; /* 100ms */
113
114 /* Use device path as the Scope for the SSDT */
115 ret = acpi_device_path(dev, path, sizeof(path));
116 if (ret)
117 return log_msg_ret("path", ret);
118 acpigen_write_scope(ctx, path);
119 acpigen_write_name(ctx, "_CRS");
120
121 /* Write GpioInt() as default (if set) or custom from devicetree */
122 acpigen_write_resourcetemplate_header(ctx);
123 acpi_device_write_gpio(ctx, &gpio);
124 acpigen_write_resourcetemplate_footer(ctx);
125
126 /* Bind the cd-gpio name to the GpioInt() resource */
127 dp = acpi_dp_new_table("_DSD");
128 if (!dp)
129 return -ENOMEM;
130 acpi_dp_add_gpio(dp, "cd-gpio", path, 0, 0, 1);
131 ret = acpi_dp_write(ctx, dp);
132 if (ret)
133 return log_msg_ret("cd", ret);
134
135 acpigen_pop_len(ctx);
136
137 return 0;
138}
139
140struct acpi_ops pci_mmc_acpi_ops = {
141 .fill_ssdt = pci_mmc_acpi_fill_ssdt,
142};
143
144static const struct udevice_id pci_mmc_match[] = {
Simon Glass60868632021-01-13 20:29:52 -0700145 { .compatible = "intel,apl-sd", .data = TYPE_SD },
146 { .compatible = "intel,apl-emmc", .data = TYPE_EMMC },
Simon Glassdba7ee42020-07-07 21:32:12 -0600147 { }
148};
149
Simon Glassb7c6bae2017-07-30 19:24:01 -0700150U_BOOT_DRIVER(pci_mmc) = {
151 .name = "pci_mmc",
152 .id = UCLASS_MMC,
Simon Glassdba7ee42020-07-07 21:32:12 -0600153 .of_match = pci_mmc_match,
Simon Glassb7c6bae2017-07-30 19:24:01 -0700154 .bind = pci_mmc_bind,
Simon Glassd1998a92020-12-03 16:55:21 -0700155 .of_to_plat = pci_mmc_of_to_plat,
Simon Glassb7c6bae2017-07-30 19:24:01 -0700156 .probe = pci_mmc_probe,
157 .ops = &sdhci_ops,
Simon Glass41575d82020-12-03 16:55:17 -0700158 .priv_auto = sizeof(struct pci_mmc_priv),
Simon Glasscaa4daa2020-12-03 16:55:18 -0700159 .plat_auto = sizeof(struct pci_mmc_plat),
Simon Glassdba7ee42020-07-07 21:32:12 -0600160 ACPI_OPS_PTR(&pci_mmc_acpi_ops)
Simon Glassb7c6bae2017-07-30 19:24:01 -0700161};
162
163static struct pci_device_id mmc_supported[] = {
Bin Menga191cca2017-08-09 00:21:00 -0700164 { PCI_DEVICE_CLASS(PCI_CLASS_SYSTEM_SDHCI << 8, 0xffff00) },
Simon Glassb7c6bae2017-07-30 19:24:01 -0700165 {},
166};
167
168U_BOOT_PCI_DEVICE(pci_mmc, mmc_supported);