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Dirk Behmef904cdb2009-01-27 18:19:12 +01001/*
2 * (C) Copyright 2006-2008
3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 *
7 * Configuration settings for the TI OMAP3530 Beagle board.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
Dirk Behmef904cdb2009-01-27 18:19:12 +010030
31/*
32 * High Level Configuration Options
33 */
Steve Sakomanf56348a2010-06-17 21:50:01 -070034#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
Dirk Behmef904cdb2009-01-27 18:19:12 +010035#define CONFIG_OMAP 1 /* in a TI OMAP core */
36#define CONFIG_OMAP34XX 1 /* which is a 34XX */
37#define CONFIG_OMAP3430 1 /* which is in a 3430 */
38#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
39
Vaibhav Hiremathcae377b2010-06-07 15:20:34 -040040#define CONFIG_SDRC /* The chip has SDRC controller */
41
Dirk Behmef904cdb2009-01-27 18:19:12 +010042#include <asm/arch/cpu.h> /* get chip and board defs */
43#include <asm/arch/omap3.h>
44
Sanjeev Premi6a6b62e2009-04-27 21:27:27 +053045/*
46 * Display CPU and Board information
47 */
48#define CONFIG_DISPLAY_CPUINFO 1
49#define CONFIG_DISPLAY_BOARDINFO 1
50
Dirk Behmef904cdb2009-01-27 18:19:12 +010051/* Clock Defines */
52#define V_OSCK 26000000 /* Clock output from T2 */
53#define V_SCLK (V_OSCK >> 1)
54
55#undef CONFIG_USE_IRQ /* no support for IRQs */
56#define CONFIG_MISC_INIT_R
57
58#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
59#define CONFIG_SETUP_MEMORY_TAGS 1
60#define CONFIG_INITRD_TAG 1
61#define CONFIG_REVISION_TAG 1
62
63/*
64 * Size of malloc() pool
65 */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -040066#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
Dirk Behmef904cdb2009-01-27 18:19:12 +010067 /* Sector */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -040068#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
Dirk Behmef904cdb2009-01-27 18:19:12 +010069#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
70 /* initial data */
71
72/*
73 * Hardware drivers
74 */
75
76/*
77 * NS16550 Configuration
78 */
79#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
80
81#define CONFIG_SYS_NS16550
82#define CONFIG_SYS_NS16550_SERIAL
83#define CONFIG_SYS_NS16550_REG_SIZE (-4)
84#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
85
86/*
87 * select serial console configuration
88 */
89#define CONFIG_CONS_INDEX 3
90#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
91#define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */
92
93/* allow to overwrite serial and ethaddr */
94#define CONFIG_ENV_OVERWRITE
95#define CONFIG_BAUDRATE 115200
96#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
97 115200}
98#define CONFIG_MMC 1
99#define CONFIG_OMAP3_MMC 1
100#define CONFIG_DOS_PARTITION 1
101
Nishanth Menon30563a02009-11-07 10:51:24 -0500102/* DDR - I use Micron DDR */
103#define CONFIG_OMAP3_MICRON_DDR 1
104
Tom Rix25374bf2009-10-31 12:37:43 -0500105/* USB */
106#define CONFIG_MUSB_UDC 1
107#define CONFIG_USB_OMAP3 1
108#define CONFIG_TWL4030_USB 1
109
110/* USB device configuration */
111#define CONFIG_USB_DEVICE 1
112#define CONFIG_USB_TTY 1
113#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
114/* Change these to suit your needs */
115#define CONFIG_USBD_VENDORID 0x0451
116#define CONFIG_USBD_PRODUCTID 0x5678
117#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
118#define CONFIG_USBD_PRODUCT_NAME "Beagle"
119
Dirk Behmef904cdb2009-01-27 18:19:12 +0100120/* commands to include */
121#include <config_cmd_default.h>
122
Heiko Schocher95c6f6d2010-09-17 13:10:31 +0200123#define CONFIG_CMD_CACHE
Dirk Behmef904cdb2009-01-27 18:19:12 +0100124#define CONFIG_CMD_EXT2 /* EXT2 Support */
125#define CONFIG_CMD_FAT /* FAT support */
126#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
Nishanth Menon917cfc72009-03-25 22:13:56 +0100127#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
Stefan Roese942556a2009-05-12 14:32:58 +0200128#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
Nishanth Menon917cfc72009-03-25 22:13:56 +0100129#define MTDIDS_DEFAULT "nand0=nand"
130#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
131 "1920k(u-boot),128k(u-boot-env),"\
132 "4m(kernel),-(fs)"
Dirk Behmef904cdb2009-01-27 18:19:12 +0100133
134#define CONFIG_CMD_I2C /* I2C serial bus support */
135#define CONFIG_CMD_MMC /* MMC support */
136#define CONFIG_CMD_NAND /* NAND support */
137
138#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
139#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
140#undef CONFIG_CMD_IMI /* iminfo */
141#undef CONFIG_CMD_IMLS /* List all found images */
142#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
143#undef CONFIG_CMD_NFS /* NFS support */
144
145#define CONFIG_SYS_NO_FLASH
Tom Rix0297ec72009-09-29 10:19:49 -0400146#define CONFIG_HARD_I2C 1
Dirk Behmef904cdb2009-01-27 18:19:12 +0100147#define CONFIG_SYS_I2C_SPEED 100000
148#define CONFIG_SYS_I2C_SLAVE 1
149#define CONFIG_SYS_I2C_BUS 0
150#define CONFIG_SYS_I2C_BUS_SELECT 1
151#define CONFIG_DRIVER_OMAP34XX_I2C 1
152
153/*
Tom Rix2c155132009-06-28 12:52:30 -0500154 * TWL4030
155 */
156#define CONFIG_TWL4030_POWER 1
157#define CONFIG_TWL4030_LED 1
158
159/*
Dirk Behmef904cdb2009-01-27 18:19:12 +0100160 * Board NAND Info.
161 */
Steve Sakoman60c23172010-08-19 20:52:35 -0700162#define CONFIG_SYS_NAND_QUIET_TEST 1
Dirk Behmef904cdb2009-01-27 18:19:12 +0100163#define CONFIG_NAND_OMAP_GPMC
164#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
165 /* to access nand */
166#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
167 /* to access nand at */
168 /* CS0 */
169#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
170
171#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
172 /* devices */
Dirk Behmef904cdb2009-01-27 18:19:12 +0100173#define CONFIG_JFFS2_NAND
174/* nand device jffs2 lives on */
175#define CONFIG_JFFS2_DEV "nand0"
176/* start of jffs2 partition */
177#define CONFIG_JFFS2_PART_OFFSET 0x680000
178#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
179 /* partition */
180
181/* Environment information */
182#define CONFIG_BOOTDELAY 10
183
184#define CONFIG_EXTRA_ENV_SETTINGS \
185 "loadaddr=0x82000000\0" \
Tom Rix25374bf2009-10-31 12:37:43 -0500186 "usbtty=cdc_acm\0" \
Dirk Behmef904cdb2009-01-27 18:19:12 +0100187 "console=ttyS2,115200n8\0" \
Steve Sakoman5af32462010-02-03 14:39:14 -0800188 "mpurate=500\0" \
Steve Sakoman13d2cb92009-10-10 14:29:37 -0400189 "vram=12M\0" \
190 "dvimode=1024x768MR-16@60\0" \
191 "defaultdisplay=dvi\0" \
192 "mmcroot=/dev/mmcblk0p2 rw\0" \
193 "mmcrootfstype=ext3 rootwait\0" \
194 "nandroot=/dev/mtdblock4 rw\0" \
195 "nandrootfstype=jffs2\0" \
Dirk Behmef904cdb2009-01-27 18:19:12 +0100196 "mmcargs=setenv bootargs console=${console} " \
Steve Sakoman5af32462010-02-03 14:39:14 -0800197 "mpurate=${mpurate} " \
Steve Sakoman13d2cb92009-10-10 14:29:37 -0400198 "vram=${vram} " \
199 "omapfb.mode=dvi:${dvimode} " \
200 "omapfb.debug=y " \
201 "omapdss.def_disp=${defaultdisplay} " \
202 "root=${mmcroot} " \
203 "rootfstype=${mmcrootfstype}\0" \
Dirk Behmef904cdb2009-01-27 18:19:12 +0100204 "nandargs=setenv bootargs console=${console} " \
Steve Sakoman5af32462010-02-03 14:39:14 -0800205 "mpurate=${mpurate} " \
Steve Sakoman13d2cb92009-10-10 14:29:37 -0400206 "vram=${vram} " \
207 "omapfb.mode=dvi:${dvimode} " \
208 "omapfb.debug=y " \
209 "omapdss.def_disp=${defaultdisplay} " \
210 "root=${nandroot} " \
211 "rootfstype=${nandrootfstype}\0" \
Dirk Behmef904cdb2009-01-27 18:19:12 +0100212 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
213 "bootscript=echo Running bootscript from mmc ...; " \
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200214 "source ${loadaddr}\0" \
Dirk Behmef904cdb2009-01-27 18:19:12 +0100215 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
216 "mmcboot=echo Booting from mmc ...; " \
217 "run mmcargs; " \
218 "bootm ${loadaddr}\0" \
219 "nandboot=echo Booting from nand ...; " \
220 "run nandargs; " \
221 "nand read ${loadaddr} 280000 400000; " \
222 "bootm ${loadaddr}\0" \
223
224#define CONFIG_BOOTCOMMAND \
Dirk Behmea85693b2009-04-21 17:30:51 +0200225 "if mmc init; then " \
Dirk Behmef904cdb2009-01-27 18:19:12 +0100226 "if run loadbootscript; then " \
227 "run bootscript; " \
228 "else " \
229 "if run loaduimage; then " \
230 "run mmcboot; " \
231 "else run nandboot; " \
232 "fi; " \
233 "fi; " \
234 "else run nandboot; fi"
235
236#define CONFIG_AUTO_COMPLETE 1
237/*
238 * Miscellaneous configurable options
239 */
Dirk Behmef904cdb2009-01-27 18:19:12 +0100240#define CONFIG_SYS_LONGHELP /* undef to save memory */
241#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
242#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Robert P. J. Day1270ec12009-12-12 12:10:33 -0500243#define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # "
Dirk Behmef904cdb2009-01-27 18:19:12 +0100244#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
245/* Print Buffer Size */
246#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
247 sizeof(CONFIG_SYS_PROMPT) + 16)
248#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
249/* Boot Argument Buffer Size */
250#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
251
252#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
253 /* works on */
254#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
255 0x01F00000) /* 31MB */
256
Dirk Behmef904cdb2009-01-27 18:19:12 +0100257#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
258 /* load address */
259
260/*
Manikandan Pillaid3a513c2009-04-21 17:29:05 +0200261 * OMAP3 has 12 GP timers, they can be driven by the system clock
262 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
263 * This rate is divided by a local divisor.
Dirk Behmef904cdb2009-01-27 18:19:12 +0100264 */
Dirk Behmef904cdb2009-01-27 18:19:12 +0100265#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
Manikandan Pillaid3a513c2009-04-21 17:29:05 +0200266#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
267#define CONFIG_SYS_HZ 1000
Dirk Behmef904cdb2009-01-27 18:19:12 +0100268
269/*-----------------------------------------------------------------------
270 * Stack sizes
271 *
272 * The stack sizes are set up in start.S using the settings below
273 */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400274#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
Dirk Behmef904cdb2009-01-27 18:19:12 +0100275#ifdef CONFIG_USE_IRQ
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400276#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
277#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
Dirk Behmef904cdb2009-01-27 18:19:12 +0100278#endif
279
280/*-----------------------------------------------------------------------
281 * Physical Memory Map
282 */
283#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
284#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400285#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
Dirk Behmef904cdb2009-01-27 18:19:12 +0100286#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
287
288/* SDRAM Bank Allocation method */
289#define SDRC_R_B_C 1
290
291/*-----------------------------------------------------------------------
292 * FLASH and environment organization
293 */
294
295/* **** PISMO SUPPORT *** */
296
297/* Configure the PISMO */
298#define PISMO1_NAND_SIZE GPMC_SIZE_128M
299#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
300
301#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
302 /* one chip */
303#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400304#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
Dirk Behmef904cdb2009-01-27 18:19:12 +0100305
306#define CONFIG_SYS_FLASH_BASE boot_flash_base
307
308/* Monitor at start of flash */
309#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
310#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
311
312#define CONFIG_ENV_IS_IN_NAND 1
313#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
314#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
315
316#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
317#define CONFIG_ENV_OFFSET boot_flash_off
318#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
319
320/*-----------------------------------------------------------------------
321 * CFI FLASH driver setup
322 */
323/* timeout values are in ticks */
324#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
325#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
326
327/* Flash banks JFFS2 should use */
328#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
329 CONFIG_SYS_MAX_NAND_DEVICE)
330#define CONFIG_SYS_JFFS2_MEM_NAND
331/* use flash_info[2] */
332#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
333#define CONFIG_SYS_JFFS2_NUM_BANKS 1
334
335#ifndef __ASSEMBLY__
Dirk Behmef904cdb2009-01-27 18:19:12 +0100336extern unsigned int boot_flash_base;
337extern volatile unsigned int boot_flash_env_addr;
338extern unsigned int boot_flash_off;
339extern unsigned int boot_flash_sec;
340extern unsigned int boot_flash_type;
341#endif
342
Heiko Schochera784c012010-09-22 14:06:33 +0200343/* additions for new relocation code, must be added to all boards */
Heiko Schocher561142a2010-09-17 13:10:41 +0200344#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
345#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
346
Dirk Behmef904cdb2009-01-27 18:19:12 +0100347#endif /* __CONFIG_H */