Matthias Weisser | 18a056a | 2010-08-09 13:31:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010 |
| 3 | * Matthias Weisser <weisserm@arcor.de> |
| 4 | * |
| 5 | * Configuation settings for the jadecpu board |
| 6 | * |
| 7 | * See file CREDITS for list of people who contributed to this |
| 8 | * project. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
| 25 | |
| 26 | #ifndef __CONFIG_H |
| 27 | #define __CONFIG_H |
| 28 | |
| 29 | #define CONFIG_MB86R0x |
| 30 | #define CONFIG_MB86R0x_IOCLK get_bus_freq(0) |
| 31 | #define CONFIG_SYS_HZ 1000 |
| 32 | |
| 33 | #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ |
| 34 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
| 35 | |
| 36 | /* |
| 37 | * Environment settings |
| 38 | */ |
| 39 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 40 | "gs_fast_boot=setenv bootdelay 5\0" \ |
| 41 | "gs_slow_boot=setenv bootdelay 10\0" \ |
| 42 | "bootcmd=mw.l 0x40000000 0 1024; usb start;" \ |
| 43 | "fatls usb 0; fatload usb 0 0x40000000 jadecpu-init.bin;" \ |
| 44 | "bootelf 0x40000000\0" \ |
| 45 | "" |
| 46 | |
| 47 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
| 48 | #define CONFIG_SETUP_MEMORY_TAGS 1 |
| 49 | #define CONFIG_INITRD_TAG 1 |
| 50 | #define BOARD_LATE_INIT 1 |
| 51 | |
| 52 | /* |
| 53 | * Compressions |
| 54 | */ |
| 55 | #define CONFIG_LZO |
| 56 | |
| 57 | /* |
| 58 | * Hardware drivers |
| 59 | */ |
| 60 | |
| 61 | /* |
| 62 | * Serial |
| 63 | */ |
| 64 | #define CONFIG_SERIAL_MULTI |
| 65 | #define CONFIG_SYS_NS16550 |
| 66 | #define CONFIG_SYS_NS16550_SERIAL |
| 67 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
| 68 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
| 69 | #define CONFIG_SYS_NS16550_COM1 0xfffe1000 /* UART 0 */ |
| 70 | #define CONFIG_SYS_NS16550_COM2 0xfff50000 /* UART 2 */ |
| 71 | #define CONFIG_SYS_NS16550_COM3 0xfff51000 /* UART 3 */ |
| 72 | #define CONFIG_SYS_NS16550_COM4 0xfff43000 /* UART 4 */ |
| 73 | |
| 74 | #define CONFIG_CONS_INDEX 4 |
| 75 | |
| 76 | /* |
| 77 | * Ethernet |
| 78 | */ |
| 79 | #define CONFIG_NET_MULTI |
| 80 | #define CONFIG_SMC911X |
| 81 | #define CONFIG_SMC911X_BASE 0x02000000 |
| 82 | #define CONFIG_SMC911X_16_BIT |
| 83 | |
| 84 | /* |
| 85 | * Video |
| 86 | */ |
| 87 | #define CONFIG_VIDEO |
| 88 | #define CONFIG_VIDEO_MB86R0xGDC |
| 89 | #define CONFIG_SYS_WHITE_ON_BLACK |
| 90 | #define CONFIG_CFB_CONSOLE |
| 91 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
| 92 | #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE |
| 93 | #define CONFIG_VIDEO_LOGO |
| 94 | #define CONFIG_SPLASH_SCREEN |
| 95 | #define CONFIG_SPLASH_SCREEN_ALIGN |
| 96 | #define CONFIG_VIDEO_BMP_LOGO |
| 97 | #define CONFIG_VIDEO_BMP_GZIP |
| 98 | #define CONFIG_VIDEO_BMP_RLE8 |
| 99 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (800*480 + 256*4 + 10*1024) |
| 100 | #define VIDEO_FB_16BPP_WORD_SWAP |
| 101 | #define VIDEO_KBD_INIT_FCT 0 |
| 102 | #define VIDEO_TSTC_FCT serial_tstc |
| 103 | #define VIDEO_GETC_FCT serial_getc |
| 104 | |
| 105 | /* |
| 106 | * BOOTP options |
| 107 | */ |
| 108 | #define CONFIG_BOOTP_BOOTFILESIZE 1 |
| 109 | #define CONFIG_BOOTP_BOOTPATH 1 |
| 110 | #define CONFIG_BOOTP_GATEWAY 1 |
| 111 | #define CONFIG_BOOTP_HOSTNAME 1 |
| 112 | |
| 113 | /* |
| 114 | * Command line configuration. |
| 115 | */ |
| 116 | #include <config_cmd_default.h> |
| 117 | #undef CONFIG_CMD_BDI |
| 118 | #undef CONFIG_CMD_FPGA |
| 119 | #undef CONFIG_CMD_IMLS |
| 120 | #undef CONFIG_CMD_LOADS |
| 121 | #undef CONFIG_CMD_SOURCE |
| 122 | #undef CONFIG_CMD_NFS |
| 123 | #undef CONFIG_CMD_XIMG |
| 124 | |
| 125 | #define CONFIG_CMD_BMP 1 |
| 126 | #define CONFIG_CMD_CAN 1 |
| 127 | #define CONFIG_CMD_DHCP 1 |
| 128 | #define CONFIG_CMD_ELF 1 |
| 129 | #define CONFIG_CMD_FAT 1 |
| 130 | #define CONFIG_CMD_PING 1 |
| 131 | #define CONFIG_CMD_USB 1 |
| 132 | |
| 133 | #define CONFIG_SYS_HUSH_PARSER |
| 134 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
| 135 | |
| 136 | /* USB */ |
| 137 | #define CONFIG_USB_OHCI_NEW |
| 138 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0xFFF81000 |
| 139 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mb86r0x" |
| 140 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 |
| 141 | #define CONFIG_USB_STORAGE |
| 142 | #define CONFIG_DOS_PARTITION |
| 143 | |
| 144 | /* SDRAM */ |
| 145 | #define CONFIG_NR_DRAM_BANKS 1 |
| 146 | #define PHYS_SDRAM 0x40000000 /* Start address of DDRRAM */ |
| 147 | #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ |
| 148 | |
Matthias Weisser | b9d74b4 | 2010-09-21 15:37:44 +0200 | [diff] [blame] | 149 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
| 150 | #define CONFIG_SYS_INIT_SP_ADDR 0x01008000 |
| 151 | |
Matthias Weisser | 18a056a | 2010-08-09 13:31:51 +0200 | [diff] [blame] | 152 | /* |
| 153 | * FLASH and environment organization |
| 154 | */ |
| 155 | #define CONFIG_SYS_FLASH_BASE 0x10000000 |
| 156 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 157 | #define CONFIG_SYS_MAX_FLASH_SECT 256 |
| 158 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 159 | |
| 160 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) |
| 161 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 162 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
| 163 | #define CONFIG_ENV_SIZE (128 * 1024) |
| 164 | |
| 165 | /* |
| 166 | * CFI FLASH driver setup |
| 167 | */ |
| 168 | #define CONFIG_SYS_FLASH_CFI 1 |
| 169 | #define CONFIG_FLASH_CFI_DRIVER 1 |
| 170 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */ |
| 171 | |
| 172 | #define CONFIG_SYS_LOAD_ADDR 0x40000000 /* load address */ |
| 173 | |
| 174 | #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024)) |
| 175 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE) |
| 176 | |
| 177 | #define CONFIG_BAUDRATE 115200 |
| 178 | #define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 } |
| 179 | |
| 180 | #define CONFIG_SYS_PROMPT "jade> " |
| 181 | #define CONFIG_SYS_CBSIZE 256 |
| 182 | #define CONFIG_SYS_MAXARGS 16 |
| 183 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| 184 | sizeof(CONFIG_SYS_PROMPT) + 16) |
| 185 | #define CONFIG_SYS_LONGHELP 1 |
| 186 | #define CONFIG_CMDLINE_EDITING 1 |
| 187 | |
| 188 | #define CONFIG_PREBOOT "" |
| 189 | |
| 190 | #define CONFIG_BOOTDELAY 5 |
| 191 | #define CONFIG_AUTOBOOT_KEYED |
| 192 | #define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay |
| 193 | #define CONFIG_AUTOBOOT_DELAY_STR "delaygs" |
| 194 | #define CONFIG_AUTOBOOT_STOP_STR "stopgs" |
| 195 | |
| 196 | /* |
| 197 | * Size of malloc() pool |
| 198 | */ |
| 199 | #define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000) |
| 200 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ |
| 201 | |
| 202 | #define CONFIG_STACKSIZE (32*1024) /* regular stack */ |
| 203 | |
| 204 | /* |
| 205 | * Clock reset generator init |
| 206 | */ |
| 207 | #define CONFIG_SYS_CRG_CRHA_INIT 0xffff |
| 208 | #define CONFIG_SYS_CRG_CRPA_INIT 0xffff |
| 209 | #define CONFIG_SYS_CRG_CRPB_INIT 0xfffe |
| 210 | #define CONFIG_SYS_CRG_CRHB_INIT 0xffff |
| 211 | #define CONFIG_SYS_CRG_CRAM_INIT 0xffef |
| 212 | |
| 213 | /* |
| 214 | * Memory controller settings |
| 215 | */ |
| 216 | #define CONFIG_SYS_MEMC_MCFMODE0_INIT 0x00000001 /* 16bit */ |
| 217 | #define CONFIG_SYS_MEMC_MCFMODE2_INIT 0x00000001 /* 16bit */ |
| 218 | #define CONFIG_SYS_MEMC_MCFMODE4_INIT 0x00000021 /* 16bit, Page*/ |
| 219 | #define CONFIG_SYS_MEMC_MCFTIM0_INIT 0x16191008 |
| 220 | #define CONFIG_SYS_MEMC_MCFTIM2_INIT 0x03061008 |
| 221 | #define CONFIG_SYS_MEMC_MCFTIM4_INIT 0x03061804 |
| 222 | #define CONFIG_SYS_MEMC_MCFAREA0_INIT 0x000000c0 /* 0x0c000000 1MB */ |
| 223 | #define CONFIG_SYS_MEMC_MCFAREA2_INIT 0x00000020 /* 0x02000000 1MB */ |
| 224 | #define CONFIG_SYS_MEMC_MCFAREA4_INIT 0x001f0000 /* 0x10000000 32 MB */ |
| 225 | |
| 226 | /* |
| 227 | * DDR2 controller init settings |
| 228 | */ |
| 229 | #define CONFIG_SYS_DDR2_DRIMS_INIT 0x5555 |
| 230 | #define CONFIG_SYS_CCNT_CDCRC_INIT_1 0x00000002 |
| 231 | #define CONFIG_SYS_CCNT_CDCRC_INIT_2 0x00000003 |
| 232 | #define CONFIG_SYS_DDR2_DRIC1_INIT 0x003f |
| 233 | #define CONFIG_SYS_DDR2_DRIC2_INIT 0x0000 |
| 234 | #define CONFIG_SYS_DDR2_DRCA_INIT 0xc124 /* 512Mbit DDR2SDRAM x 2 */ |
| 235 | #define CONFIG_SYS_DDR2_DRCM_INIT 0x0032 |
| 236 | #define CONFIG_SYS_DDR2_DRCST1_INIT 0x3418 |
| 237 | #define CONFIG_SYS_DDR2_DRCST2_INIT 0x6e32 |
| 238 | #define CONFIG_SYS_DDR2_DRCR_INIT 0x0141 |
| 239 | #define CONFIG_SYS_DDR2_DRCF_INIT 0x0002 |
| 240 | #define CONFIG_SYS_DDR2_DRASR_INIT 0x0001 |
| 241 | #define CONFIG_SYS_DDR2_DROBS_INIT 0x0001 |
| 242 | #define CONFIG_SYS_DDR2_DROABA_INIT 0x0103 |
| 243 | #define CONFIG_SYS_DDR2_DRIBSODT1_INIT 0x003F |
| 244 | #define CONFIG_SYS_DDR2_DROS_INIT 0x0001 |
| 245 | |
| 246 | /* |
| 247 | * DRAM init sequence |
| 248 | */ |
| 249 | |
| 250 | /* PALL Command */ |
| 251 | #define CONFIG_SYS_DDR2_INIT_DRIC1_1 0x0017 |
| 252 | #define CONFIG_SYS_DDR2_INIT_DRIC2_1 0x0400 |
| 253 | |
| 254 | /* EMR(2) command */ |
| 255 | #define CONFIG_SYS_DDR2_INIT_DRIC1_2 0x0006 |
| 256 | #define CONFIG_SYS_DDR2_INIT_DRIC2_2 0x0000 |
| 257 | |
| 258 | /* EMR(3) command */ |
| 259 | #define CONFIG_SYS_DDR2_INIT_DRIC1_3 0x0007 |
| 260 | #define CONFIG_SYS_DDR2_INIT_DRIC2_3 0x0000 |
| 261 | |
| 262 | /* EMR(1) command */ |
| 263 | #define CONFIG_SYS_DDR2_INIT_DRIC1_4 0x0005 |
| 264 | #define CONFIG_SYS_DDR2_INIT_DRIC2_4 0x0000 |
| 265 | |
| 266 | /* MRS command */ |
| 267 | #define CONFIG_SYS_DDR2_INIT_DRIC1_5 0x0004 |
| 268 | #define CONFIG_SYS_DDR2_INIT_DRIC2_5 0x0532 |
| 269 | |
| 270 | /* PALL command */ |
| 271 | #define CONFIG_SYS_DDR2_INIT_DRIC1_6 0x0017 |
| 272 | #define CONFIG_SYS_DDR2_INIT_DRIC2_6 0x0400 |
| 273 | |
| 274 | /* REF command 1 */ |
| 275 | #define CONFIG_SYS_DDR2_INIT_DRIC1_7 0x000f |
| 276 | #define CONFIG_SYS_DDR2_INIT_DRIC2_7 0x0000 |
| 277 | |
| 278 | /* MRS command */ |
| 279 | #define CONFIG_SYS_DDR2_INIT_DRIC1_8 0x0004 |
| 280 | #define CONFIG_SYS_DDR2_INIT_DRIC2_8 0x0432 |
| 281 | |
| 282 | /* EMR(1) command */ |
| 283 | #define CONFIG_SYS_DDR2_INIT_DRIC1_9 0x0005 |
| 284 | #define CONFIG_SYS_DDR2_INIT_DRIC2_9 0x0380 |
| 285 | |
| 286 | /* EMR(1) command */ |
| 287 | #define CONFIG_SYS_DDR2_INIT_DRIC1_10 0x0005 |
| 288 | #define CONFIG_SYS_DDR2_INIT_DRIC2_10 0x0002 |
| 289 | |
| 290 | #ifdef CONFIG_USE_IRQ |
| 291 | #error CONFIG_USE_IRQ not supported |
| 292 | #endif |
| 293 | |
| 294 | #endif /* __CONFIG_H */ |