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Hans de Goeded6e6d4b2015-11-20 16:03:56 +01001/*
2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "skeleton.dtsi"
44
45#include <dt-bindings/interrupt-controller/arm-gic.h>
46#include <dt-bindings/pinctrl/sun4i-a10.h>
47
48/ {
49 interrupt-parent = <&gic>;
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54
55 cpu@0 {
56 compatible = "arm,cortex-a7";
57 device_type = "cpu";
58 reg = <0>;
59 };
60
61 cpu@1 {
62 compatible = "arm,cortex-a7";
63 device_type = "cpu";
64 reg = <1>;
65 };
66
67 cpu@2 {
68 compatible = "arm,cortex-a7";
69 device_type = "cpu";
70 reg = <2>;
71 };
72
73 cpu@3 {
74 compatible = "arm,cortex-a7";
75 device_type = "cpu";
76 reg = <3>;
77 };
78 };
79
80 timer {
81 compatible = "arm,armv7-timer";
82 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
83 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
84 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
85 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +010086 };
87
88 clocks {
89 #address-cells = <1>;
90 #size-cells = <1>;
91 ranges;
92
93 osc24M: osc24M_clk {
94 #clock-cells = <0>;
95 compatible = "fixed-clock";
96 clock-frequency = <24000000>;
97 clock-output-names = "osc24M";
98 };
99
100 osc32k: osc32k_clk {
101 #clock-cells = <0>;
102 compatible = "fixed-clock";
103 clock-frequency = <32768>;
104 clock-output-names = "osc32k";
105 };
106
107 pll1: clk@01c20000 {
108 #clock-cells = <0>;
109 compatible = "allwinner,sun8i-a23-pll1-clk";
110 reg = <0x01c20000 0x4>;
111 clocks = <&osc24M>;
112 clock-output-names = "pll1";
113 };
114
115 /* dummy clock until actually implemented */
116 pll5: pll5_clk {
117 #clock-cells = <0>;
118 compatible = "fixed-clock";
119 clock-frequency = <0>;
120 clock-output-names = "pll5";
121 };
122
123 pll6: clk@01c20028 {
124 #clock-cells = <1>;
125 compatible = "allwinner,sun6i-a31-pll6-clk";
126 reg = <0x01c20028 0x4>;
127 clocks = <&osc24M>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100128 clock-output-names = "pll6", "pll6x2";
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100129 };
130
Hans de Goede80e5f832016-03-14 17:37:09 +0100131 pll6d2: pll6d2_clk {
132 #clock-cells = <0>;
133 compatible = "fixed-factor-clock";
134 clock-div = <2>;
135 clock-mult = <1>;
136 clocks = <&pll6 0>;
137 clock-output-names = "pll6d2";
138 };
139
140 /* dummy clock until pll6 can be reused */
141 pll8: pll8_clk {
142 #clock-cells = <0>;
143 compatible = "fixed-clock";
144 clock-frequency = <1>;
145 clock-output-names = "pll8";
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100146 };
147
148 cpu: cpu_clk@01c20050 {
149 #clock-cells = <0>;
150 compatible = "allwinner,sun4i-a10-cpu-clk";
151 reg = <0x01c20050 0x4>;
152 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
153 clock-output-names = "cpu";
154 };
155
156 axi: axi_clk@01c20050 {
157 #clock-cells = <0>;
158 compatible = "allwinner,sun4i-a10-axi-clk";
159 reg = <0x01c20050 0x4>;
160 clocks = <&cpu>;
161 clock-output-names = "axi";
162 };
163
164 ahb1: ahb1_clk@01c20054 {
165 #clock-cells = <0>;
166 compatible = "allwinner,sun6i-a31-ahb1-clk";
167 reg = <0x01c20054 0x4>;
168 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
169 clock-output-names = "ahb1";
170 };
171
172 ahb2: ahb2_clk@01c2005c {
173 #clock-cells = <0>;
174 compatible = "allwinner,sun8i-h3-ahb2-clk";
175 reg = <0x01c2005c 0x4>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100176 clocks = <&ahb1>, <&pll6d2>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100177 clock-output-names = "ahb2";
178 };
179
180 apb1: apb1_clk@01c20054 {
181 #clock-cells = <0>;
182 compatible = "allwinner,sun4i-a10-apb0-clk";
183 reg = <0x01c20054 0x4>;
184 clocks = <&ahb1>;
185 clock-output-names = "apb1";
186 };
187
188 apb2: apb2_clk@01c20058 {
189 #clock-cells = <0>;
190 compatible = "allwinner,sun4i-a10-apb1-clk";
191 reg = <0x01c20058 0x4>;
192 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
193 clock-output-names = "apb2";
194 };
195
196 bus_gates: clk@01c20060 {
197 #clock-cells = <1>;
198 compatible = "allwinner,sun8i-h3-bus-gates-clk";
199 reg = <0x01c20060 0x14>;
200 clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
201 clock-names = "ahb1", "ahb2", "apb1", "apb2";
202 clock-indices = <5>, <6>, <8>,
203 <9>, <10>, <13>,
204 <14>, <17>, <18>,
205 <19>, <20>,
206 <21>, <23>,
207 <24>, <25>,
208 <26>, <27>,
209 <28>, <29>,
210 <30>, <31>, <32>,
211 <35>, <36>, <37>,
212 <40>, <41>, <43>,
213 <44>, <52>, <53>,
214 <54>, <64>,
215 <65>, <69>, <72>,
216 <76>, <77>, <78>,
217 <96>, <97>, <98>,
218 <112>, <113>,
Hans de Goede80e5f832016-03-14 17:37:09 +0100219 <114>, <115>,
220 <116>, <128>, <135>;
221 clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
222 "bus_mmc1", "bus_mmc2", "bus_nand",
223 "bus_sdram", "bus_gmac", "bus_ts",
224 "bus_hstimer", "bus_spi0",
225 "bus_spi1", "bus_otg",
226 "bus_otg_ehci0", "bus_ehci1",
227 "bus_ehci2", "bus_ehci3",
228 "bus_otg_ohci0", "bus_ohci1",
229 "bus_ohci2", "bus_ohci3", "bus_ve",
230 "bus_lcd0", "bus_lcd1", "bus_deint",
231 "bus_csi", "bus_tve", "bus_hdmi",
232 "bus_de", "bus_gpu", "bus_msgbox",
233 "bus_spinlock", "bus_codec",
234 "bus_spdif", "bus_pio", "bus_ths",
235 "bus_i2s0", "bus_i2s1", "bus_i2s2",
236 "bus_i2c0", "bus_i2c1", "bus_i2c2",
237 "bus_uart0", "bus_uart1",
238 "bus_uart2", "bus_uart3",
239 "bus_scr", "bus_ephy", "bus_dbg";
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100240 };
241
242 mmc0_clk: clk@01c20088 {
243 #clock-cells = <1>;
244 compatible = "allwinner,sun4i-a10-mmc-clk";
245 reg = <0x01c20088 0x4>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100246 clocks = <&osc24M>, <&pll6 0>, <&pll8>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100247 clock-output-names = "mmc0",
248 "mmc0_output",
249 "mmc0_sample";
250 };
251
252 mmc1_clk: clk@01c2008c {
253 #clock-cells = <1>;
254 compatible = "allwinner,sun4i-a10-mmc-clk";
255 reg = <0x01c2008c 0x4>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100256 clocks = <&osc24M>, <&pll6 0>, <&pll8>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100257 clock-output-names = "mmc1",
258 "mmc1_output",
259 "mmc1_sample";
260 };
261
262 mmc2_clk: clk@01c20090 {
263 #clock-cells = <1>;
264 compatible = "allwinner,sun4i-a10-mmc-clk";
265 reg = <0x01c20090 0x4>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100266 clocks = <&osc24M>, <&pll6 0>, <&pll8>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100267 clock-output-names = "mmc2",
268 "mmc2_output",
269 "mmc2_sample";
270 };
271
272 usb_clk: clk@01c200cc {
273 #clock-cells = <1>;
274 #reset-cells = <1>;
275 compatible = "allwinner,sun8i-h3-usb-clk";
276 reg = <0x01c200cc 0x4>;
277 clocks = <&osc24M>;
278 clock-output-names = "usb_phy0", "usb_phy1",
279 "usb_phy2", "usb_phy3",
280 "usb_ohci0", "usb_ohci1",
281 "usb_ohci2", "usb_ohci3";
282 };
283
284 mbus_clk: clk@01c2015c {
285 #clock-cells = <0>;
286 compatible = "allwinner,sun8i-a23-mbus-clk";
287 reg = <0x01c2015c 0x4>;
288 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
289 clock-output-names = "mbus";
290 };
Hans de Goede80e5f832016-03-14 17:37:09 +0100291
292 apb0: apb0_clk {
293 compatible = "fixed-factor-clock";
294 #clock-cells = <0>;
295 clock-div = <1>;
296 clock-mult = <1>;
297 clocks = <&osc24M>;
298 clock-output-names = "apb0";
299 };
300
301 apb0_gates: clk@01f01428 {
302 compatible = "allwinner,sun8i-h3-apb0-gates-clk",
303 "allwinner,sun4i-a10-gates-clk";
304 reg = <0x01f01428 0x4>;
305 #clock-cells = <1>;
306 clocks = <&apb0>;
307 clock-indices = <0>, <1>;
308 clock-output-names = "apb0_pio", "apb0_ir";
309 };
310
311 ir_clk: ir_clk@01f01454 {
312 compatible = "allwinner,sun4i-a10-mod0-clk";
313 reg = <0x01f01454 0x4>;
314 #clock-cells = <0>;
315 clocks = <&osc32k>, <&osc24M>;
316 clock-output-names = "ir";
317 };
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100318 };
319
320 soc {
321 compatible = "simple-bus";
322 #address-cells = <1>;
323 #size-cells = <1>;
324 ranges;
325
326 dma: dma-controller@01c02000 {
327 compatible = "allwinner,sun8i-h3-dma";
328 reg = <0x01c02000 0x1000>;
329 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&bus_gates 6>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100331 resets = <&ahb_rst 6>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100332 #dma-cells = <1>;
333 };
334
335 mmc0: mmc@01c0f000 {
336 compatible = "allwinner,sun5i-a13-mmc";
337 reg = <0x01c0f000 0x1000>;
338 clocks = <&bus_gates 8>,
339 <&mmc0_clk 0>,
340 <&mmc0_clk 1>,
341 <&mmc0_clk 2>;
342 clock-names = "ahb",
343 "mmc",
344 "output",
345 "sample";
Hans de Goede80e5f832016-03-14 17:37:09 +0100346 resets = <&ahb_rst 8>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100347 reset-names = "ahb";
348 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
349 status = "disabled";
350 #address-cells = <1>;
351 #size-cells = <0>;
352 };
353
354 mmc1: mmc@01c10000 {
355 compatible = "allwinner,sun5i-a13-mmc";
356 reg = <0x01c10000 0x1000>;
357 clocks = <&bus_gates 9>,
358 <&mmc1_clk 0>,
359 <&mmc1_clk 1>,
360 <&mmc1_clk 2>;
361 clock-names = "ahb",
362 "mmc",
363 "output",
364 "sample";
Hans de Goede80e5f832016-03-14 17:37:09 +0100365 resets = <&ahb_rst 9>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100366 reset-names = "ahb";
367 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
368 status = "disabled";
369 #address-cells = <1>;
370 #size-cells = <0>;
371 };
372
373 mmc2: mmc@01c11000 {
374 compatible = "allwinner,sun5i-a13-mmc";
375 reg = <0x01c11000 0x1000>;
376 clocks = <&bus_gates 10>,
377 <&mmc2_clk 0>,
378 <&mmc2_clk 1>,
379 <&mmc2_clk 2>;
380 clock-names = "ahb",
381 "mmc",
382 "output",
383 "sample";
Hans de Goede80e5f832016-03-14 17:37:09 +0100384 resets = <&ahb_rst 10>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100385 reset-names = "ahb";
386 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
387 status = "disabled";
388 #address-cells = <1>;
389 #size-cells = <0>;
390 };
391
392 usbphy: phy@01c19400 {
393 compatible = "allwinner,sun8i-h3-usb-phy";
394 reg = <0x01c19400 0x2c>,
395 <0x01c1a800 0x4>,
396 <0x01c1b800 0x4>,
397 <0x01c1c800 0x4>,
398 <0x01c1d800 0x4>;
399 reg-names = "phy_ctrl",
400 "pmu0",
401 "pmu1",
402 "pmu2",
403 "pmu3";
404 clocks = <&usb_clk 8>,
405 <&usb_clk 9>,
406 <&usb_clk 10>,
407 <&usb_clk 11>;
408 clock-names = "usb0_phy",
409 "usb1_phy",
410 "usb2_phy",
411 "usb3_phy";
412 resets = <&usb_clk 0>,
413 <&usb_clk 1>,
414 <&usb_clk 2>,
415 <&usb_clk 3>;
416 reset-names = "usb0_reset",
417 "usb1_reset",
418 "usb2_reset",
419 "usb3_reset";
420 status = "disabled";
421 #phy-cells = <1>;
422 };
423
424 ehci1: usb@01c1b000 {
425 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
426 reg = <0x01c1b000 0x100>;
427 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&bus_gates 25>, <&bus_gates 29>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100429 resets = <&ahb_rst 25>, <&ahb_rst 29>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100430 phys = <&usbphy 1>;
431 phy-names = "usb";
432 status = "disabled";
433 };
434
435 ohci1: usb@01c1b400 {
436 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
437 reg = <0x01c1b400 0x100>;
438 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&bus_gates 29>, <&bus_gates 25>,
440 <&usb_clk 17>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100441 resets = <&ahb_rst 29>, <&ahb_rst 25>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100442 phys = <&usbphy 1>;
443 phy-names = "usb";
444 status = "disabled";
445 };
446
447 ehci2: usb@01c1c000 {
448 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
449 reg = <0x01c1c000 0x100>;
450 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&bus_gates 26>, <&bus_gates 30>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100452 resets = <&ahb_rst 26>, <&ahb_rst 30>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100453 phys = <&usbphy 2>;
454 phy-names = "usb";
455 status = "disabled";
456 };
457
458 ohci2: usb@01c1c400 {
459 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
460 reg = <0x01c1c400 0x100>;
461 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&bus_gates 30>, <&bus_gates 26>,
463 <&usb_clk 18>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100464 resets = <&ahb_rst 30>, <&ahb_rst 26>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100465 phys = <&usbphy 2>;
466 phy-names = "usb";
467 status = "disabled";
468 };
469
470 ehci3: usb@01c1d000 {
471 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
472 reg = <0x01c1d000 0x100>;
473 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&bus_gates 27>, <&bus_gates 31>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100475 resets = <&ahb_rst 27>, <&ahb_rst 31>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100476 phys = <&usbphy 3>;
477 phy-names = "usb";
478 status = "disabled";
479 };
480
481 ohci3: usb@01c1d400 {
482 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
483 reg = <0x01c1d400 0x100>;
484 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&bus_gates 31>, <&bus_gates 27>,
486 <&usb_clk 19>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100487 resets = <&ahb_rst 31>, <&ahb_rst 27>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100488 phys = <&usbphy 3>;
489 phy-names = "usb";
490 status = "disabled";
491 };
492
493 pio: pinctrl@01c20800 {
494 compatible = "allwinner,sun8i-h3-pinctrl";
495 reg = <0x01c20800 0x400>;
496 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&bus_gates 69>;
499 gpio-controller;
500 #gpio-cells = <3>;
501 interrupt-controller;
Hans de Goede80e5f832016-03-14 17:37:09 +0100502 #interrupt-cells = <3>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100503
504 uart0_pins_a: uart0@0 {
505 allwinner,pins = "PA4", "PA5";
506 allwinner,function = "uart0";
507 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
508 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
509 };
510
511 mmc0_pins_a: mmc0@0 {
512 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
513 "PF4", "PF5";
514 allwinner,function = "mmc0";
515 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
516 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
517 };
518
519 mmc0_cd_pin: mmc0_cd_pin@0 {
520 allwinner,pins = "PF6";
521 allwinner,function = "gpio_in";
522 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
523 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
524 };
525
526 mmc1_pins_a: mmc1@0 {
527 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
528 "PG4", "PG5";
529 allwinner,function = "mmc1";
530 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
531 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
532 };
533 };
534
Hans de Goede80e5f832016-03-14 17:37:09 +0100535 ahb_rst: reset@01c202c0 {
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100536 #reset-cells = <1>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100537 compatible = "allwinner,sun6i-a31-ahb1-reset";
538 reg = <0x01c202c0 0xc>;
539 };
540
541 apb1_rst: reset@01c202d0 {
542 #reset-cells = <1>;
543 compatible = "allwinner,sun6i-a31-clock-reset";
544 reg = <0x01c202d0 0x4>;
545 };
546
547 apb2_rst: reset@01c202d8 {
548 #reset-cells = <1>;
549 compatible = "allwinner,sun6i-a31-clock-reset";
550 reg = <0x01c202d8 0x4>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100551 };
552
553 timer@01c20c00 {
554 compatible = "allwinner,sun4i-a10-timer";
555 reg = <0x01c20c00 0xa0>;
556 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&osc24M>;
559 };
560
561 wdt0: watchdog@01c20ca0 {
562 compatible = "allwinner,sun6i-a31-wdt";
563 reg = <0x01c20ca0 0x20>;
564 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
565 };
566
567 uart0: serial@01c28000 {
568 compatible = "snps,dw-apb-uart";
569 reg = <0x01c28000 0x400>;
570 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
571 reg-shift = <2>;
572 reg-io-width = <4>;
573 clocks = <&bus_gates 112>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100574 resets = <&apb2_rst 16>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100575 dmas = <&dma 6>, <&dma 6>;
576 dma-names = "rx", "tx";
577 status = "disabled";
578 };
579
580 uart1: serial@01c28400 {
581 compatible = "snps,dw-apb-uart";
582 reg = <0x01c28400 0x400>;
583 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
584 reg-shift = <2>;
585 reg-io-width = <4>;
586 clocks = <&bus_gates 113>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100587 resets = <&apb2_rst 17>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100588 dmas = <&dma 7>, <&dma 7>;
589 dma-names = "rx", "tx";
590 status = "disabled";
591 };
592
593 uart2: serial@01c28800 {
594 compatible = "snps,dw-apb-uart";
595 reg = <0x01c28800 0x400>;
596 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
597 reg-shift = <2>;
598 reg-io-width = <4>;
599 clocks = <&bus_gates 114>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100600 resets = <&apb2_rst 18>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100601 dmas = <&dma 8>, <&dma 8>;
602 dma-names = "rx", "tx";
603 status = "disabled";
604 };
605
606 uart3: serial@01c28c00 {
607 compatible = "snps,dw-apb-uart";
608 reg = <0x01c28c00 0x400>;
609 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
610 reg-shift = <2>;
611 reg-io-width = <4>;
612 clocks = <&bus_gates 115>;
Hans de Goede80e5f832016-03-14 17:37:09 +0100613 resets = <&apb2_rst 19>;
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100614 dmas = <&dma 9>, <&dma 9>;
615 dma-names = "rx", "tx";
616 status = "disabled";
617 };
618
619 gic: interrupt-controller@01c81000 {
620 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
621 reg = <0x01c81000 0x1000>,
622 <0x01c82000 0x1000>,
623 <0x01c84000 0x2000>,
624 <0x01c86000 0x2000>;
625 interrupt-controller;
626 #interrupt-cells = <3>;
627 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
628 };
629
630 rtc: rtc@01f00000 {
631 compatible = "allwinner,sun6i-a31-rtc";
632 reg = <0x01f00000 0x54>;
633 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
634 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
635 };
Hans de Goede80e5f832016-03-14 17:37:09 +0100636
637 apb0_reset: reset@01f014b0 {
638 reg = <0x01f014b0 0x4>;
639 compatible = "allwinner,sun6i-a31-clock-reset";
640 #reset-cells = <1>;
641 };
642
643 ir: ir@01f02000 {
644 compatible = "allwinner,sun5i-a13-ir";
645 clocks = <&apb0_gates 1>, <&ir_clk>;
646 clock-names = "apb", "ir";
647 resets = <&apb0_reset 1>;
648 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
649 reg = <0x01f02000 0x40>;
650 status = "disabled";
651 };
652
653 r_pio: pinctrl@01f02c00 {
654 compatible = "allwinner,sun8i-h3-r-pinctrl";
655 reg = <0x01f02c00 0x400>;
656 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&apb0_gates 0>;
658 resets = <&apb0_reset 0>;
659 gpio-controller;
660 #gpio-cells = <3>;
661 interrupt-controller;
662 #interrupt-cells = <3>;
663
664 ir_pins_a: ir@0 {
665 allwinner,pins = "PL11";
666 allwinner,function = "s_cir_rx";
667 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
668 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
669 };
670 };
Hans de Goeded6e6d4b2015-11-20 16:03:56 +0100671 };
672};