| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #include <ppc_asm.tmpl> |
| 24 | #include <config.h> |
| Stefan Roese | 8423e5e | 2007-03-16 21:11:42 +0100 | [diff] [blame] | 25 | #include <asm-ppc/mmu.h> |
| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 26 | |
| 27 | /************************************************************************** |
| 28 | * TLB TABLE |
| 29 | * |
| 30 | * This table is used by the cpu boot code to setup the initial tlb |
| 31 | * entries. Rather than make broad assumptions in the cpu source tree, |
| 32 | * this table lets each board set things up however they like. |
| 33 | * |
| 34 | * Pointer to the table is returned in r1 |
| 35 | * |
| 36 | *************************************************************************/ |
| 37 | |
| Stefan Roese | 8423e5e | 2007-03-16 21:11:42 +0100 | [diff] [blame] | 38 | .section .bootpg,"ax" |
| 39 | .globl tlbtab |
| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 40 | |
| 41 | tlbtab: |
| Stefan Roese | 8423e5e | 2007-03-16 21:11:42 +0100 | [diff] [blame] | 42 | tlbtab_start |
| 43 | |
| 44 | tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) |
| 45 | |
| 46 | /* |
| 47 | * TLB entries for SDRAM are not needed on this platform. |
| 48 | * They are dynamically generated in the SPD DDR(2) detection |
| 49 | * routine. |
| 50 | */ |
| 51 | |
| 52 | tlbentry(CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) |
| 53 | tlbentry(CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X) |
| 54 | tlbentry(CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X) |
| 55 | tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I) |
| 56 | tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I) |
| 57 | tlbtab_end |