blob: e05dd75cecb1441dc9086710a04bc10116f74b9c [file] [log] [blame]
Kumar Galae02aea62011-02-09 02:00:08 +00001/*
2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Galae02aea62011-02-09 02:00:08 +00005 */
6
7/*
8 * P3041 DS board configuration file
9 *
10 */
11#define CONFIG_P3041DS
12#define CONFIG_PHYS_64BIT
13#define CONFIG_PPC_P3041
14
Kumar Galac6d33902011-08-31 09:50:13 -050015#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
16
17#define CONFIG_MMC
18#define CONFIG_NAND_FSL_ELBC
Zang Roy-R619119760b272012-11-26 00:05:38 +000019#define CONFIG_FSL_SATA_V2
Kumar Galac6d33902011-08-31 09:50:13 -050020#define CONFIG_PCIE3
Kumar Galae02aea62011-02-09 02:00:08 +000021#define CONFIG_PCIE4
Kumar Gala4d28db82011-10-14 13:28:52 -050022#define CONFIG_SYS_DPAA_RMAN
Kumar Galae02aea62011-02-09 02:00:08 +000023
Timur Tabi11860d82012-10-05 09:48:53 +000024#define CONFIG_SYS_SRIO
25#define CONFIG_SRIO1 /* SRIO port 1 */
26#define CONFIG_SRIO2 /* SRIO port 2 */
Liu Gangc8b28152013-05-07 16:30:46 +080027#define CONFIG_SRIO_PCIE_BOOT_MASTER
Kumar Galae02aea62011-02-09 02:00:08 +000028#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
29
30#include "corenet_ds.h"