blob: 355e892457d49b88744b24ebdadcbd5f1c2ede79 [file] [log] [blame]
Marek Vasut237ce0f2011-08-28 03:35:13 +02001/*
2 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 */
19
20#ifndef __REGS_UART_H__
21#define __REGS_UART_H__
22
23#define FFUART_BASE 0x40100000
24#define BTUART_BASE 0x40200000
25#define STUART_BASE 0x40700000
26#define HWUART_BASE 0x41600000
27
28struct pxa_uart_regs {
29 union {
30 uint32_t thr;
31 uint32_t rbr;
32 uint32_t dll;
33 };
34 union {
35 uint32_t ier;
36 uint32_t dlh;
37 };
38 union {
39 uint32_t fcr;
40 uint32_t iir;
41 };
42 uint32_t lcr;
43 uint32_t mcr;
44 uint32_t lsr;
45 uint32_t msr;
46 uint32_t spr;
47 uint32_t isr;
48};
49
50#define IER_DMAE (1 << 7)
51#define IER_UUE (1 << 6)
52#define IER_NRZE (1 << 5)
53#define IER_RTIOE (1 << 4)
54#define IER_MIE (1 << 3)
55#define IER_RLSE (1 << 2)
56#define IER_TIE (1 << 1)
57#define IER_RAVIE (1 << 0)
58
59#define IIR_FIFOES1 (1 << 7)
60#define IIR_FIFOES0 (1 << 6)
61#define IIR_TOD (1 << 3)
62#define IIR_IID2 (1 << 2)
63#define IIR_IID1 (1 << 1)
64#define IIR_IP (1 << 0)
65
66#define FCR_ITL2 (1 << 7)
67#define FCR_ITL1 (1 << 6)
68#define FCR_RESETTF (1 << 2)
69#define FCR_RESETRF (1 << 1)
70#define FCR_TRFIFOE (1 << 0)
71#define FCR_ITL_1 0
72#define FCR_ITL_8 (FCR_ITL1)
73#define FCR_ITL_16 (FCR_ITL2)
74#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
75
76#define LCR_DLAB (1 << 7)
77#define LCR_SB (1 << 6)
78#define LCR_STKYP (1 << 5)
79#define LCR_EPS (1 << 4)
80#define LCR_PEN (1 << 3)
81#define LCR_STB (1 << 2)
82#define LCR_WLS1 (1 << 1)
83#define LCR_WLS0 (1 << 0)
84
85#define LSR_FIFOE (1 << 7)
86#define LSR_TEMT (1 << 6)
87#define LSR_TDRQ (1 << 5)
88#define LSR_BI (1 << 4)
89#define LSR_FE (1 << 3)
90#define LSR_PE (1 << 2)
91#define LSR_OE (1 << 1)
92#define LSR_DR (1 << 0)
93
94#define MCR_LOOP (1 << 4)
95#define MCR_OUT2 (1 << 3)
96#define MCR_OUT1 (1 << 2)
97#define MCR_RTS (1 << 1)
98#define MCR_DTR (1 << 0)
99
100#define MSR_DCD (1 << 7)
101#define MSR_RI (1 << 6)
102#define MSR_DSR (1 << 5)
103#define MSR_CTS (1 << 4)
104#define MSR_DDCD (1 << 3)
105#define MSR_TERI (1 << 2)
106#define MSR_DDSR (1 << 1)
107#define MSR_DCTS (1 << 0)
108
109#endif /* __REGS_UART_H__ */