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Niklaus Giger75a66dc2008-02-25 18:46:42 +01001/*
2 *(C) Copyright 2005-2007 Netstal Maschinen AG
3 * Niklaus Giger (Niklaus.Giger@netstal.com)
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/************************************************************************
25 * mcu25.h - configuration for MCU25 board (similar to hcu4.h)
26 ***********************************************************************/
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*-----------------------------------------------------------------------
32 * High Level Configuration Options
33 *----------------------------------------------------------------------*/
34#define CONFIG_MCU25 1 /* Board is MCU25 */
35#define CONFIG_4xx 1 /* ... PPC4xx family */
36#define CONFIG_405GP 1
37#define CONFIG_4xx 1
Niklaus Gigerc11da192008-10-01 14:46:13 +020038#define CONFIG_HOSTNAME mcu25
39
40/*
41 * Include common defines/options for all boards produced by Netstal Maschinen
42 */
43#include "netstal-common.h"
Niklaus Giger75a66dc2008-02-25 18:46:42 +010044
45#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
46
47#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
48#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
49
50/*-----------------------------------------------------------------------
51 * Base addresses -- Note these are effective addresses where the
52 * actual resources get mapped (not physical addresses)
53*----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
55#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
Niklaus Giger75a66dc2008-02-25 18:46:42 +010056
57
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
59#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
60#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
Niklaus Giger75a66dc2008-02-25 18:46:42 +010061
62/* ... with on-chip memory here (4KBytes) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000
64#define CONFIG_SYS_OCM_DATA_SIZE 0x00001000
Niklaus Giger75a66dc2008-02-25 18:46:42 +010065/* Do not set up locked dcache as init ram. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#undef CONFIG_SYS_INIT_DCACHE_CS
Niklaus Giger75a66dc2008-02-25 18:46:42 +010067
68/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_TEMP_STACK_OCM 1
Niklaus Giger75a66dc2008-02-25 18:46:42 +010070
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* OCM */
72#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
73#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
74#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
Michael Zaidman800eb092010-09-20 08:51:53 +020075#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
Niklaus Giger75a66dc2008-02-25 18:46:42 +010076
77/*-----------------------------------------------------------------------
78 * Serial Port
79 *----------------------------------------------------------------------*/
80/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
82 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
83 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
Niklaus Giger75a66dc2008-02-25 18:46:42 +010084 * The Linux BASE_BAUD define should match this configuration.
85 * baseBaud = cpuClock/(uartDivisor*16)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
Niklaus Giger75a66dc2008-02-25 18:46:42 +010087 * set Linux BASE_BAUD to 403200.
88 */
Niklaus Giger75a66dc2008-02-25 18:46:42 +010089/* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
91#define CONFIG_SYS_BASE_BAUD 691200
Niklaus Giger75a66dc2008-02-25 18:46:42 +010092
93/* Size (bytes) of interrupt driven serial port buffer.
94 * Set to 0 to use polling instead of interrupts.
95 * Setting to 0 will also disable RTS/CTS handshaking.
96 */
97#undef CONFIG_SERIAL_SOFTWARE_FIFO
98
99/* Set console baudrate to 9600 */
100#define CONFIG_BAUDRATE 9600
101
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100102/*-----------------------------------------------------------------------
103 * Flash
104 *----------------------------------------------------------------------*/
105
106/* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200108#define CONFIG_FLASH_CFI_DRIVER
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100109/* board provides its own flash_init code */
110#define CONFIG_FLASH_CFI_LEGACY 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
112#define CONFIG_SYS_FLASH_LEGACY_512Kx8 1
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100113
114/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_FLASH_EMPTY_INFO
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
118#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100119
120/*-----------------------------------------------------------------------
121 * Environment
122 *----------------------------------------------------------------------*/
123
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200124#undef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200125#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200126#undef CONFIG_ENV_IS_NOWHERE
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100127
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200128#ifdef CONFIG_ENV_IS_IN_EEPROM
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100129/* Put the environment after the SDRAM configuration */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200130#define PROM_SIZE 2048
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200131#define CONFIG_ENV_OFFSET 512
132#define CONFIG_ENV_SIZE (PROM_SIZE-CONFIG_ENV_OFFSET)
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100133#endif
134
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200135#ifdef CONFIG_ENV_IS_IN_FLASH
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100136/* Put the environment in Flash */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200137#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200139#define CONFIG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100140
141/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200142#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
143#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100144#endif
145
146/*-----------------------------------------------------------------------
147 * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
148 * the first internal I2C controller of the PPC440EPx
149 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_SPD_BUS_NUM 0
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100151
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100152/* Setup some board specific values for the default environment variables */
Niklaus Gigerc11da192008-10-01 14:46:13 +0200153#define CONFIG_IPADDR 172.25.1.25
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100154
Niklaus Gigerc11da192008-10-01 14:46:13 +0200155#define CONFIG_EXTRA_ENV_SETTINGS \
156 CONFIG_NETSTAL_DEF_ENV \
157 CONFIG_NETSTAL_DEF_ENV_POWERPC \
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100158 ""
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100159
160/*
161 * BOOTP options
162 */
163#define CONFIG_BOOTP_BOOTFILESIZE
164#define CONFIG_BOOTP_BOOTPATH
165#define CONFIG_BOOTP_GATEWAY
166#define CONFIG_BOOTP_HOSTNAME
167
168/*
169 * Command line configuration.
170 */
171#include <config_cmd_default.h>
172
173#define CONFIG_CMD_ASKENV
174#define CONFIG_CMD_CACHE
175#define CONFIG_CMD_DHCP
176#define CONFIG_CMD_DIAG
177#define CONFIG_CMD_EEPROM
178#define CONFIG_CMD_ELF
179#define CONFIG_CMD_FLASH
180#define CONFIG_CMD_I2C
181#define CONFIG_CMD_IMMAP
182#define CONFIG_CMD_IRQ
183#define CONFIG_CMD_MII
184#define CONFIG_CMD_NET
185#define CONFIG_CMD_PING
186#define CONFIG_CMD_REGINFO
187#define CONFIG_CMD_SDRAM
188
189/* SPD EEPROM (sdram speed config) disabled */
190#define CONFIG_SPD_EEPROM 1
191#define SPD_EEPROM_ADDRESS 0x50
192
193/* POST support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
195 CONFIG_SYS_POST_CPU | \
196 CONFIG_SYS_POST_UART | \
197 CONFIG_SYS_POST_I2C | \
198 CONFIG_SYS_POST_CACHE | \
199 CONFIG_SYS_POST_ETHER | \
200 CONFIG_SYS_POST_SPR)
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE}
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100203#undef CONFIG_LOGBUFFER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
205#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100206
207/*-----------------------------------------------------------------------
208 * Miscellaneous configurable options
209 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_LONGHELP /* undef to save memory */
211#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100212#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100214#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100216#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
218#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
219#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
222#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100223
224
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100226
227/*-----------------------------------------------------------------------
228 * External Bus Controller (EBC) Setup
229 */
230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_EBC_CFG 0x98400000
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100232
233/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_EBC_PB0AP 0x02005400
235#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit*/
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_EBC_PB1AP 0x03041200
238#define CONFIG_SYS_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_EBC_PB2AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */
241#define CONFIG_SYS_EBC_PB2CR 0x7A09A000u
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_EBC_PB3AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */
244#define CONFIG_SYS_EBC_PB3CR 0x7B09A000u
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_EBC_PB4AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */
247#define CONFIG_SYS_EBC_PB4CR 0x7C09A000u
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_EBC_PB5AP 0x00800200u
250#define CONFIG_SYS_EBC_PB5CR 0x7D81A000u
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_EBC_PB6AP 0x01040200u
253#define CONFIG_SYS_EBC_PB6CR 0x7D91A000u
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100254
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_GPIO0_OR 0x087FFFFF /* GPIO value */
256#define CONFIG_SYS_GPIO0_TCR 0x7FFF8000 /* GPIO value */
257#define CONFIG_SYS_GPIO0_ODR 0xFFFF0000 /* GPIO value */
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100258/*
259 * For booting Linux, the board info and command line data
260 * have to be in the first 8 MB of memory, since this is
261 * the maximum mapped by the Linux kernel during initialization.
262 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100264
265/* Init Memory Controller:
266 *
267 * BR0/1 and OR0/1 (FLASH)
268 */
269
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100271#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
272
273
274/* Configuration Port location */
275#define CONFIG_PORT_ADDR 0xF0000500
276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
278#ifdef CONFIG_SYS_HUSH_PARSER
279#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100280#endif
281
282#if defined(CONFIG_CMD_KGDB)
283#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
284#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
285#endif
286
Niklaus Giger75a66dc2008-02-25 18:46:42 +0100287#endif /* __CONFIG_H */