| Andy Fleming | 5f18471 | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 1 | /* |
| 2 | * linux/mdio.h: definitions for MDIO (clause 45) transceivers |
| 3 | * Copyright 2006-2009 Solarflare Communications Inc. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License version 2 as published |
| 7 | * by the Free Software Foundation, incorporated herein by reference. |
| 8 | */ |
| 9 | |
| 10 | #ifndef __LINUX_MDIO_H__ |
| 11 | #define __LINUX_MDIO_H__ |
| 12 | |
| 13 | #include <linux/mii.h> |
| 14 | |
| 15 | /* MDIO Manageable Devices (MMDs). */ |
| 16 | #define MDIO_MMD_PMAPMD 1 /* Physical Medium Attachment/ |
| 17 | * Physical Medium Dependent */ |
| 18 | #define MDIO_MMD_WIS 2 /* WAN Interface Sublayer */ |
| 19 | #define MDIO_MMD_PCS 3 /* Physical Coding Sublayer */ |
| 20 | #define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */ |
| 21 | #define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */ |
| 22 | #define MDIO_MMD_TC 6 /* Transmission Convergence */ |
| 23 | #define MDIO_MMD_AN 7 /* Auto-Negotiation */ |
| 24 | #define MDIO_MMD_C22EXT 29 /* Clause 22 extension */ |
| 25 | #define MDIO_MMD_VEND1 30 /* Vendor specific 1 */ |
| 26 | #define MDIO_MMD_VEND2 31 /* Vendor specific 2 */ |
| 27 | |
| 28 | /* Generic MDIO registers. */ |
| 29 | #define MDIO_CTRL1 MII_BMCR |
| 30 | #define MDIO_STAT1 MII_BMSR |
| 31 | #define MDIO_DEVID1 MII_PHYSID1 |
| 32 | #define MDIO_DEVID2 MII_PHYSID2 |
| 33 | #define MDIO_SPEED 4 /* Speed ability */ |
| 34 | #define MDIO_DEVS1 5 /* Devices in package */ |
| 35 | #define MDIO_DEVS2 6 |
| 36 | #define MDIO_CTRL2 7 /* 10G control 2 */ |
| 37 | #define MDIO_STAT2 8 /* 10G status 2 */ |
| 38 | #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */ |
| 39 | #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */ |
| 40 | #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */ |
| 41 | #define MDIO_PKGID1 14 /* Package identifier */ |
| 42 | #define MDIO_PKGID2 15 |
| 43 | #define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */ |
| 44 | #define MDIO_AN_LPA 19 /* AN LP abilities (base page) */ |
| 45 | #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */ |
| 46 | |
| 47 | /* Media-dependent registers. */ |
| 48 | #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */ |
| 49 | #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */ |
| 50 | #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A. |
| 51 | * Lanes B-D are numbered 134-136. */ |
| 52 | #define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */ |
| 53 | #define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */ |
| 54 | #define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */ |
| 55 | #define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */ |
| 56 | #define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */ |
| 57 | #define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */ |
| 58 | #define MDIO_AN_EEE_ADV 60 /* EEE advertisement */ |
| 59 | |
| 60 | /* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */ |
| 61 | #define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */ |
| 62 | #define MDIO_PMA_LASI_TXCTRL 0x9001 /* TX_ALARM control */ |
| 63 | #define MDIO_PMA_LASI_CTRL 0x9002 /* LASI control */ |
| 64 | #define MDIO_PMA_LASI_RXSTAT 0x9003 /* RX_ALARM status */ |
| 65 | #define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */ |
| 66 | #define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */ |
| 67 | |
| 68 | /* Control register 1. */ |
| 69 | /* Enable extended speed selection */ |
| 70 | #define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100) |
| 71 | /* All speed selection bits */ |
| 72 | #define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c) |
| 73 | #define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX |
| 74 | #define MDIO_CTRL1_LPOWER BMCR_PDOWN |
| 75 | #define MDIO_CTRL1_RESET BMCR_RESET |
| 76 | #define MDIO_PMA_CTRL1_LOOPBACK 0x0001 |
| 77 | #define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000 |
| 78 | #define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100 |
| 79 | #define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK |
| 80 | #define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK |
| 81 | #define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART |
| 82 | #define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE |
| 83 | #define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */ |
| 84 | |
| 85 | /* 10 Gb/s */ |
| 86 | #define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00) |
| 87 | /* 10PASS-TS/2BASE-TL */ |
| 88 | #define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04) |
| 89 | |
| 90 | /* Status register 1. */ |
| 91 | #define MDIO_STAT1_LPOWERABLE 0x0002 /* Low-power ability */ |
| 92 | #define MDIO_STAT1_LSTATUS BMSR_LSTATUS |
| 93 | #define MDIO_STAT1_FAULT 0x0080 /* Fault */ |
| 94 | #define MDIO_AN_STAT1_LPABLE 0x0001 /* Link partner AN ability */ |
| 95 | #define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE |
| 96 | #define MDIO_AN_STAT1_RFAULT BMSR_RFAULT |
| 97 | #define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE |
| 98 | #define MDIO_AN_STAT1_PAGE 0x0040 /* Page received */ |
| 99 | #define MDIO_AN_STAT1_XNP 0x0080 /* Extended next page status */ |
| 100 | |
| 101 | /* Speed register. */ |
| 102 | #define MDIO_SPEED_10G 0x0001 /* 10G capable */ |
| 103 | #define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */ |
| 104 | #define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */ |
| 105 | #define MDIO_PMA_SPEED_1000 0x0010 /* 1000M capable */ |
| 106 | #define MDIO_PMA_SPEED_100 0x0020 /* 100M capable */ |
| 107 | #define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */ |
| 108 | #define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */ |
| 109 | |
| 110 | /* Device present registers. */ |
| 111 | #define MDIO_DEVS_PRESENT(devad) (1 << (devad)) |
| 112 | #define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD) |
| 113 | #define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS) |
| 114 | #define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS) |
| 115 | #define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS) |
| 116 | #define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS) |
| 117 | #define MDIO_DEVS_TC MDIO_DEVS_PRESENT(MDIO_MMD_TC) |
| 118 | #define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN) |
| 119 | #define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT) |
| 120 | #define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1) |
| 121 | #define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2) |
| 122 | |
| Andy Fleming | ee8fa20 | 2011-05-18 13:44:19 +0000 | [diff] [blame] | 123 | #define MDIO_DEVS_LINK (MDIO_DEVS_PMAPMD | \ |
| 124 | MDIO_DEVS_WIS | \ |
| 125 | MDIO_DEVS_PCS | \ |
| 126 | MDIO_DEVS_PHYXS | \ |
| 127 | MDIO_DEVS_DTEXS | \ |
| 128 | MDIO_DEVS_AN) |
| 129 | |
| Andy Fleming | 5f18471 | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 130 | /* Control register 2. */ |
| 131 | #define MDIO_PMA_CTRL2_TYPE 0x000f /* PMA/PMD type selection */ |
| 132 | #define MDIO_PMA_CTRL2_10GBCX4 0x0000 /* 10GBASE-CX4 type */ |
| 133 | #define MDIO_PMA_CTRL2_10GBEW 0x0001 /* 10GBASE-EW type */ |
| 134 | #define MDIO_PMA_CTRL2_10GBLW 0x0002 /* 10GBASE-LW type */ |
| 135 | #define MDIO_PMA_CTRL2_10GBSW 0x0003 /* 10GBASE-SW type */ |
| 136 | #define MDIO_PMA_CTRL2_10GBLX4 0x0004 /* 10GBASE-LX4 type */ |
| 137 | #define MDIO_PMA_CTRL2_10GBER 0x0005 /* 10GBASE-ER type */ |
| 138 | #define MDIO_PMA_CTRL2_10GBLR 0x0006 /* 10GBASE-LR type */ |
| 139 | #define MDIO_PMA_CTRL2_10GBSR 0x0007 /* 10GBASE-SR type */ |
| 140 | #define MDIO_PMA_CTRL2_10GBLRM 0x0008 /* 10GBASE-LRM type */ |
| 141 | #define MDIO_PMA_CTRL2_10GBT 0x0009 /* 10GBASE-T type */ |
| 142 | #define MDIO_PMA_CTRL2_10GBKX4 0x000a /* 10GBASE-KX4 type */ |
| 143 | #define MDIO_PMA_CTRL2_10GBKR 0x000b /* 10GBASE-KR type */ |
| 144 | #define MDIO_PMA_CTRL2_1000BT 0x000c /* 1000BASE-T type */ |
| 145 | #define MDIO_PMA_CTRL2_1000BKX 0x000d /* 1000BASE-KX type */ |
| 146 | #define MDIO_PMA_CTRL2_100BTX 0x000e /* 100BASE-TX type */ |
| 147 | #define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */ |
| 148 | #define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */ |
| 149 | #define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */ |
| 150 | #define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */ |
| 151 | #define MDIO_PCS_CTRL2_10GBW 0x0002 /* 10GBASE-W type */ |
| 152 | #define MDIO_PCS_CTRL2_10GBT 0x0003 /* 10GBASE-T type */ |
| 153 | |
| 154 | /* Status register 2. */ |
| 155 | #define MDIO_STAT2_RXFAULT 0x0400 /* Receive fault */ |
| 156 | #define MDIO_STAT2_TXFAULT 0x0800 /* Transmit fault */ |
| 157 | #define MDIO_STAT2_DEVPRST 0xc000 /* Device present */ |
| 158 | #define MDIO_STAT2_DEVPRST_VAL 0x8000 /* Device present value */ |
| 159 | #define MDIO_PMA_STAT2_LBABLE 0x0001 /* PMA loopback ability */ |
| 160 | #define MDIO_PMA_STAT2_10GBEW 0x0002 /* 10GBASE-EW ability */ |
| 161 | #define MDIO_PMA_STAT2_10GBLW 0x0004 /* 10GBASE-LW ability */ |
| 162 | #define MDIO_PMA_STAT2_10GBSW 0x0008 /* 10GBASE-SW ability */ |
| 163 | #define MDIO_PMA_STAT2_10GBLX4 0x0010 /* 10GBASE-LX4 ability */ |
| 164 | #define MDIO_PMA_STAT2_10GBER 0x0020 /* 10GBASE-ER ability */ |
| 165 | #define MDIO_PMA_STAT2_10GBLR 0x0040 /* 10GBASE-LR ability */ |
| 166 | #define MDIO_PMA_STAT2_10GBSR 0x0080 /* 10GBASE-SR ability */ |
| 167 | #define MDIO_PMD_STAT2_TXDISAB 0x0100 /* PMD TX disable ability */ |
| 168 | #define MDIO_PMA_STAT2_EXTABLE 0x0200 /* Extended abilities */ |
| 169 | #define MDIO_PMA_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */ |
| 170 | #define MDIO_PMA_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */ |
| 171 | #define MDIO_PCS_STAT2_10GBR 0x0001 /* 10GBASE-R capable */ |
| 172 | #define MDIO_PCS_STAT2_10GBX 0x0002 /* 10GBASE-X capable */ |
| 173 | #define MDIO_PCS_STAT2_10GBW 0x0004 /* 10GBASE-W capable */ |
| 174 | #define MDIO_PCS_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */ |
| 175 | #define MDIO_PCS_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */ |
| 176 | |
| 177 | /* Transmit disable register. */ |
| 178 | #define MDIO_PMD_TXDIS_GLOBAL 0x0001 /* Global PMD TX disable */ |
| 179 | #define MDIO_PMD_TXDIS_0 0x0002 /* PMD TX disable 0 */ |
| 180 | #define MDIO_PMD_TXDIS_1 0x0004 /* PMD TX disable 1 */ |
| 181 | #define MDIO_PMD_TXDIS_2 0x0008 /* PMD TX disable 2 */ |
| 182 | #define MDIO_PMD_TXDIS_3 0x0010 /* PMD TX disable 3 */ |
| 183 | |
| 184 | /* Receive signal detect register. */ |
| 185 | #define MDIO_PMD_RXDET_GLOBAL 0x0001 /* Global PMD RX signal detect */ |
| 186 | #define MDIO_PMD_RXDET_0 0x0002 /* PMD RX signal detect 0 */ |
| 187 | #define MDIO_PMD_RXDET_1 0x0004 /* PMD RX signal detect 1 */ |
| 188 | #define MDIO_PMD_RXDET_2 0x0008 /* PMD RX signal detect 2 */ |
| 189 | #define MDIO_PMD_RXDET_3 0x0010 /* PMD RX signal detect 3 */ |
| 190 | |
| 191 | /* Extended abilities register. */ |
| 192 | #define MDIO_PMA_EXTABLE_10GCX4 0x0001 /* 10GBASE-CX4 ability */ |
| 193 | #define MDIO_PMA_EXTABLE_10GBLRM 0x0002 /* 10GBASE-LRM ability */ |
| 194 | #define MDIO_PMA_EXTABLE_10GBT 0x0004 /* 10GBASE-T ability */ |
| 195 | #define MDIO_PMA_EXTABLE_10GBKX4 0x0008 /* 10GBASE-KX4 ability */ |
| 196 | #define MDIO_PMA_EXTABLE_10GBKR 0x0010 /* 10GBASE-KR ability */ |
| 197 | #define MDIO_PMA_EXTABLE_1000BT 0x0020 /* 1000BASE-T ability */ |
| 198 | #define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */ |
| 199 | #define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */ |
| 200 | #define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */ |
| 201 | |
| 202 | /* PHY XGXS lane state register. */ |
| 203 | #define MDIO_PHYXS_LNSTAT_SYNC0 0x0001 |
| 204 | #define MDIO_PHYXS_LNSTAT_SYNC1 0x0002 |
| 205 | #define MDIO_PHYXS_LNSTAT_SYNC2 0x0004 |
| 206 | #define MDIO_PHYXS_LNSTAT_SYNC3 0x0008 |
| 207 | #define MDIO_PHYXS_LNSTAT_ALIGN 0x1000 |
| 208 | |
| 209 | /* PMA 10GBASE-T pair swap & polarity */ |
| 210 | #define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001 /* Pair A/B uncrossed */ |
| 211 | #define MDIO_PMA_10GBT_SWAPPOL_CDNX 0x0002 /* Pair C/D uncrossed */ |
| 212 | #define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100 /* Pair A polarity reversed */ |
| 213 | #define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200 /* Pair B polarity reversed */ |
| 214 | #define MDIO_PMA_10GBT_SWAPPOL_CREV 0x0400 /* Pair C polarity reversed */ |
| 215 | #define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800 /* Pair D polarity reversed */ |
| 216 | |
| 217 | /* PMA 10GBASE-T TX power register. */ |
| 218 | #define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 /* Short-reach mode */ |
| 219 | |
| 220 | /* PMA 10GBASE-T SNR registers. */ |
| 221 | /* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */ |
| 222 | #define MDIO_PMA_10GBT_SNR_BIAS 0x8000 |
| 223 | #define MDIO_PMA_10GBT_SNR_MAX 127 |
| 224 | |
| 225 | /* PMA 10GBASE-R FEC ability register. */ |
| 226 | #define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */ |
| 227 | #define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability */ |
| 228 | |
| 229 | /* PCS 10GBASE-R/-T status register 1. */ |
| 230 | #define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001 /* Block lock attained */ |
| 231 | |
| 232 | /* PCS 10GBASE-R/-T status register 2. */ |
| 233 | #define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff |
| 234 | #define MDIO_PCS_10GBRT_STAT2_BER 0x3f00 |
| 235 | |
| 236 | /* AN 10GBASE-T control register. */ |
| 237 | #define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */ |
| 238 | |
| 239 | /* AN 10GBASE-T status register. */ |
| 240 | #define MDIO_AN_10GBT_STAT_LPTRR 0x0200 /* LP training reset req. */ |
| 241 | #define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400 /* LP loop timing ability */ |
| 242 | #define MDIO_AN_10GBT_STAT_LP10G 0x0800 /* LP is 10GBT capable */ |
| 243 | #define MDIO_AN_10GBT_STAT_REMOK 0x1000 /* Remote OK */ |
| 244 | #define MDIO_AN_10GBT_STAT_LOCOK 0x2000 /* Local OK */ |
| 245 | #define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */ |
| 246 | #define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */ |
| 247 | |
| 248 | /* AN EEE Advertisement register. */ |
| 249 | #define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */ |
| 250 | #define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */ |
| 251 | |
| 252 | /* LASI RX_ALARM control/status registers. */ |
| 253 | #define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */ |
| 254 | #define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */ |
| 255 | #define MDIO_PMA_LASI_RX_PMALFLT 0x0010 /* PMA/PMD RX local fault */ |
| 256 | #define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020 /* RX optical power fault */ |
| 257 | #define MDIO_PMA_LASI_RX_WISLFLT 0x0200 /* WIS local fault */ |
| 258 | |
| 259 | /* LASI TX_ALARM control/status registers. */ |
| 260 | #define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001 /* PHY XS TX local fault */ |
| 261 | #define MDIO_PMA_LASI_TX_PCSLFLT 0x0008 /* PCS TX local fault */ |
| 262 | #define MDIO_PMA_LASI_TX_PMALFLT 0x0010 /* PMA/PMD TX local fault */ |
| 263 | #define MDIO_PMA_LASI_TX_LASERPOWERFLT 0x0080 /* Laser output power fault */ |
| 264 | #define MDIO_PMA_LASI_TX_LASERTEMPFLT 0x0100 /* Laser temperature fault */ |
| 265 | #define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200 /* Laser bias current fault */ |
| 266 | |
| 267 | /* LASI control/status registers. */ |
| 268 | #define MDIO_PMA_LASI_LSALARM 0x0001 /* LS_ALARM enable/status */ |
| 269 | #define MDIO_PMA_LASI_TXALARM 0x0002 /* TX_ALARM enable/status */ |
| 270 | #define MDIO_PMA_LASI_RXALARM 0x0004 /* RX_ALARM enable/status */ |
| 271 | |
| 272 | /* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */ |
| 273 | |
| 274 | #define MDIO_PHY_ID_C45 0x8000 |
| 275 | #define MDIO_PHY_ID_PRTAD 0x03e0 |
| 276 | #define MDIO_PHY_ID_DEVAD 0x001f |
| 277 | #define MDIO_PHY_ID_C45_MASK \ |
| 278 | (MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD) |
| 279 | |
| 280 | #define MDIO_PRTAD_NONE (-1) |
| 281 | #define MDIO_DEVAD_NONE (-1) |
| 282 | #define MDIO_EMULATE_C22 4 |
| 283 | |
| 284 | #endif /* __LINUX_MDIO_H__ */ |