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Andre Przywara0e4d5db2016-08-23 22:19:30 +01001/*
2 * Utility functions for FEL mode, when running SPL in AArch64.
3 *
4 * Copyright (c) 2017 Arm Ltd.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <asm-offsets.h>
10#include <config.h>
11#include <asm/system.h>
12#include <linux/linkage.h>
Andre Przywarabeeace92022-07-03 00:14:24 +010013#include <asm/arch/cpu.h>
Andre Przywara0e4d5db2016-08-23 22:19:30 +010014
15/*
16 * We don't overwrite save_boot_params() here, to save the FEL state upon
17 * entry, since this would run *after* the RMR reset, which clobbers that
18 * state.
19 * Instead we store the state _very_ early in the boot0 hook, *before*
20 * resetting to AArch64.
21 */
22
23/*
24 * The FEL routines in BROM run in AArch32.
25 * Reset back into 32-bit mode here and restore the saved FEL state
26 * afterwards.
27 * Resetting back into AArch32/EL3 using the RMR always enters the BROM,
28 * but we can use the CPU hotplug mechanism to branch back to our code
29 * immediately.
30 */
31ENTRY(return_to_fel)
32 /*
33 * the RMR reset will clear all registers, so save the arguments
34 * (LR and SP) in the fel_stash structure, which we read anyways later
35 */
36 adr x2, fel_stash
37 str w0, [x2]
38 str w1, [x2, #4]
39
40 adr x1, fel_stash_addr // to find the fel_stash address in AA32
41 str w2, [x1]
42
Andre Przywara48716502022-07-13 16:27:56 +010043 ldr w0, =0xfa50392f // CPU hotplug magic
Jernej Skrabec3d594ef2021-01-11 21:11:48 +010044#ifdef CONFIG_MACH_SUN50I_H616
Andre Przywara48716502022-07-13 16:27:56 +010045 ldr w2, =(SUNXI_R_CPUCFG_BASE + 0x1c0)
Jernej Skrabec3d594ef2021-01-11 21:11:48 +010046 str w0, [x2], #0x4
47#elif CONFIG_MACH_SUN50I_H6
Andre Przywara48716502022-07-13 16:27:56 +010048 ldr w2, =(SUNXI_RTC_BASE + 0x1b8) // BOOT_CPU_HP_FLAG_REG
Andre Przywara0e4d5db2016-08-23 22:19:30 +010049 str w0, [x2], #0x4
50#else
Andre Przywara48716502022-07-13 16:27:56 +010051 ldr w2, =(SUNXI_CPUCFG_BASE + 0x1a4) // offset for CPU hotplug base
Andre Przywara0e4d5db2016-08-23 22:19:30 +010052 str w0, [x2, #0x8]
53#endif
54 adr x0, back_in_32
55 str w0, [x2]
56
57 dsb sy
58 isb sy
59 mov x0, #2 // RMR reset into AArch32
60 dsb sy
61 msr RMR_EL3, x0
62 isb sy
631: wfi
64 b 1b
65
66/* AArch32 code to restore the state from fel_stash and return back to FEL. */
67back_in_32:
Wolfgang Denk0cf207e2021-09-27 17:42:39 +020068 .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address
69 .word 0xe5901008 // ldr r1, [r0, #8]
70 .word 0xe129f001 // msr CPSR_fc, r1
Andre Przywara0e4d5db2016-08-23 22:19:30 +010071 .word 0xf57ff06f // isb
Wolfgang Denk0cf207e2021-09-27 17:42:39 +020072 .word 0xe590d000 // ldr sp, [r0]
73 .word 0xe590e004 // ldr lr, [r0, #4]
74 .word 0xe5901010 // ldr r1, [r0, #16]
75 .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR
76 .word 0xe590100c // ldr r1, [r0, #12]
77 .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR
Andre Przywara0e4d5db2016-08-23 22:19:30 +010078 .word 0xf57ff06f // isb
Wolfgang Denk0cf207e2021-09-27 17:42:39 +020079 .word 0xe12fff1e // bx lr ; return to FEL
Andre Przywara0e4d5db2016-08-23 22:19:30 +010080fel_stash_addr:
81 .word 0x00000000 // receives fel_stash addr, by AA64 code above
82ENDPROC(return_to_fel)