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Lokesh Vutlaa66b9142021-05-06 16:45:00 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
Kishon Vijay Abraham I326ee2b2021-10-20 21:09:12 +05308#include <dt-bindings/mux/ti-serdes.h>
9#include <dt-bindings/phy/phy.h>
Vignesh Raghavendraef7be5a2021-12-24 12:55:35 +053010#include <dt-bindings/net/ti-dp83867.h>
Lokesh Vutlaa66b9142021-05-06 16:45:00 +053011#include "k3-am642.dtsi"
Dave Gerlach8359b992022-09-29 12:35:48 -050012#include "k3-am64-sk-lp4-1600MTs.dtsi"
Lokesh Vutlaa66b9142021-05-06 16:45:00 +053013#include "k3-am64-ddr.dtsi"
14
15/ {
16 chosen {
17 stdout-path = "serial2:115200n8";
18 tick-timer = &timer1;
19 };
20
21 aliases {
22 remoteproc0 = &sysctrler;
23 remoteproc1 = &a53_0;
24 };
25
26 memory@80000000 {
27 device_type = "memory";
28 /* 2G RAM */
29 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
Simon Glass8c103c32023-02-13 08:56:33 -070030 bootph-pre-ram;
Lokesh Vutlaa66b9142021-05-06 16:45:00 +053031 };
32
33 a53_0: a53@0 {
34 compatible = "ti,am654-rproc";
35 reg = <0x00 0x00a90000 0x00 0x10>;
36 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
Manorit Chawdhry7fe79202023-04-14 09:47:56 +053037 <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
38 <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
Lokesh Vutlaa66b9142021-05-06 16:45:00 +053039 resets = <&k3_reset 135 0>;
40 clocks = <&k3_clks 61 0>;
41 assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
42 assigned-clock-parents = <&k3_clks 61 2>;
43 assigned-clock-rates = <200000000>, <1000000000>;
44 ti,sci = <&dmsc>;
45 ti,sci-proc-id = <32>;
46 ti,sci-host-id = <10>;
Simon Glass8c103c32023-02-13 08:56:33 -070047 bootph-pre-ram;
Lokesh Vutlaa66b9142021-05-06 16:45:00 +053048 };
49
50 reserved-memory {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 ranges;
54
55 secure_ddr: optee@9e800000 {
56 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
57 alignment = <0x1000>;
58 no-map;
59 };
60 };
61
62 clk_200mhz: dummy-clock-200mhz {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <200000000>;
Simon Glass8c103c32023-02-13 08:56:33 -070066 bootph-pre-ram;
Lokesh Vutlaa66b9142021-05-06 16:45:00 +053067 };
68};
69
70&cbass_main {
71 sysctrler: sysctrler {
72 compatible = "ti,am654-system-controller";
73 mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
74 mbox-names = "tx", "rx";
Simon Glass8c103c32023-02-13 08:56:33 -070075 bootph-pre-ram;
Lokesh Vutlaa66b9142021-05-06 16:45:00 +053076 };
77};
78
Hari Nagalla3d64cff2022-03-09 14:42:29 -060079&cbass_main {
80 main_esm: esm@420000 {
81 compatible = "ti,j721e-esm";
82 reg = <0x0 0x420000 0x0 0x1000>;
83 ti,esm-pins = <160>, <161>;
Simon Glass8c103c32023-02-13 08:56:33 -070084 bootph-pre-ram;
Hari Nagalla3d64cff2022-03-09 14:42:29 -060085 };
86};
87
88&cbass_mcu {
Simon Glass8c103c32023-02-13 08:56:33 -070089 bootph-pre-ram;
Hari Nagalla3d64cff2022-03-09 14:42:29 -060090 mcu_esm: esm@4100000 {
91 compatible = "ti,j721e-esm";
92 reg = <0x0 0x4100000 0x0 0x1000>;
93 ti,esm-pins = <0>, <1>;
Simon Glass8c103c32023-02-13 08:56:33 -070094 bootph-pre-ram;
Hari Nagalla3d64cff2022-03-09 14:42:29 -060095 };
96};
97
Lokesh Vutlaa66b9142021-05-06 16:45:00 +053098&main_pmx0 {
Simon Glass8c103c32023-02-13 08:56:33 -070099 bootph-pre-ram;
Lokesh Vutlaa66b9142021-05-06 16:45:00 +0530100 main_uart0_pins_default: main-uart0-pins-default {
Simon Glass8c103c32023-02-13 08:56:33 -0700101 bootph-pre-ram;
Lokesh Vutlaa66b9142021-05-06 16:45:00 +0530102 pinctrl-single,pins = <
103 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
104 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
105 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
106 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
107 >;
108 };
109
110 main_uart1_pins_default: main-uart1-pins-default {
Simon Glass8c103c32023-02-13 08:56:33 -0700111 bootph-pre-ram;
Lokesh Vutlaa66b9142021-05-06 16:45:00 +0530112 pinctrl-single,pins = <
113 AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
114 AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
115 AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
116 AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
117 >;
118 };
119
120 main_mmc1_pins_default: main-mmc1-pins-default {
Simon Glass8c103c32023-02-13 08:56:33 -0700121 bootph-pre-ram;
Lokesh Vutlaa66b9142021-05-06 16:45:00 +0530122 pinctrl-single,pins = <
123 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
124 AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
125 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
126 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
127 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
128 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
129 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
130 AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
131 >;
132 };
Kishon Vijay Abraham I326ee2b2021-10-20 21:09:12 +0530133
134 main_usb0_pins_default: main-usb0-pins-default {
Simon Glass8c103c32023-02-13 08:56:33 -0700135 bootph-pre-ram;
Kishon Vijay Abraham I326ee2b2021-10-20 21:09:12 +0530136 pinctrl-single,pins = <
137 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
138 >;
139 };
Vignesh Raghavendraef7be5a2021-12-24 12:55:35 +0530140
141 mdio1_pins_default: mdio1-pins-default {
142 pinctrl-single,pins = <
143 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
144 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
145 >;
146 };
147
148 rgmii1_pins_default: rgmii1-pins-default {
149 pinctrl-single,pins = <
150 AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
151 AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
152 AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
153 AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
154 AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
155 AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
156 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
157 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
158 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
159 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
160 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
161 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
162 >;
163 };
164
165 rgmii2_pins_default: rgmii2-pins-default {
166 pinctrl-single,pins = <
167 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
168 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
169 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
170 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
171 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
172 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
173 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
174 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
175 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
176 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
177 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
178 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
179 >;
180 };
Lokesh Vutlaa66b9142021-05-06 16:45:00 +0530181};
182
183&dmsc {
184 mboxes= <&secure_proxy_main 0>,
185 <&secure_proxy_main 1>,
186 <&secure_proxy_main 0>;
187 mbox-names = "rx", "tx", "notify";
188 ti,host-id = <35>;
189 ti,secure-host;
190};
191
192&main_uart0 {
193 /delete-property/ power-domains;
194 /delete-property/ clocks;
195 /delete-property/ clock-names;
196 pinctrl-names = "default";
197 pinctrl-0 = <&main_uart0_pins_default>;
198 status = "okay";
199};
200
201&main_uart1 {
Simon Glass8c103c32023-02-13 08:56:33 -0700202 bootph-pre-ram;
Lokesh Vutlaa66b9142021-05-06 16:45:00 +0530203 pinctrl-names = "default";
204 pinctrl-0 = <&main_uart1_pins_default>;
205};
206
207&sdhci1 {
208 /delete-property/ power-domains;
209 clocks = <&clk_200mhz>;
210 clock-names = "clk_xin";
211 ti,driver-strength-ohm = <50>;
212 disable-wp;
213 pinctrl-0 = <&main_mmc1_pins_default>;
214};
215
Kishon Vijay Abraham I326ee2b2021-10-20 21:09:12 +0530216&serdes_ln_ctrl {
217 idle-states = <AM64_SERDES0_LANE0_USB>;
218};
219
220&serdes_wiz0 {
221 status = "okay";
222};
223
224&serdes0 {
225 serdes0_usb_link: link@0 {
226 reg = <0>;
227 cdns,num-lanes = <1>;
228 #phy-cells = <0>;
229 cdns,phy-type = <PHY_TYPE_USB3>;
230 resets = <&serdes_wiz0 1>;
231 };
232};
233
234&usbss0 {
235 ti,vbus-divider;
236};
237
238&usb0 {
239 dr_mode = "host";
240 maximum-speed = "super-speed";
241 pinctrl-names = "default";
242 pinctrl-0 = <&main_usb0_pins_default>;
243 phys = <&serdes0_usb_link>;
244 phy-names = "cdns3,usb3-phy";
245};
246
Vignesh Raghavendraef7be5a2021-12-24 12:55:35 +0530247&cpsw3g {
248 pinctrl-names = "default";
249 pinctrl-0 = <&mdio1_pins_default
250 &rgmii1_pins_default
251 &rgmii2_pins_default>;
252};
253
Vignesh Raghavendraef7be5a2021-12-24 12:55:35 +0530254&cpsw_port2 {
255 phy-mode = "rgmii-rxid";
256 phy-handle = <&cpsw3g_phy1>;
257};
258
259&cpsw3g_mdio {
Vignesh Raghavendraef7be5a2021-12-24 12:55:35 +0530260 cpsw3g_phy1: ethernet-phy@1 {
261 reg = <1>;
262 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
263 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
264 };
265};
266
Lokesh Vutlaa66b9142021-05-06 16:45:00 +0530267#include "k3-am642-sk-u-boot.dtsi"