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Matt Porter1d0933e2013-10-07 15:53:02 +05301/*
2 * TI QSPI driver
3 *
4 * Copyright (C) 2013, Texas Instruments, Incorporated
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <asm/io.h>
11#include <asm/arch/omap.h>
12#include <malloc.h>
13#include <spi.h>
Mugunthan V N106f8132015-12-23 20:39:40 +053014#include <dm.h>
Sourav Poddar570533b2013-12-21 12:50:09 +053015#include <asm/gpio.h>
16#include <asm/omap_gpio.h>
Vignesh R8ddd9c42015-08-17 15:20:13 +053017#include <asm/omap_common.h>
18#include <asm/ti-common/ti-edma3.h>
Vignesh R948b8bb2016-11-05 16:05:16 +053019#include <linux/kernel.h>
Jean-Jacques Hiblotb06a3812017-02-13 16:17:49 +010020#include <regmap.h>
21#include <syscon.h>
Matt Porter1d0933e2013-10-07 15:53:02 +053022
Mugunthan V N106f8132015-12-23 20:39:40 +053023DECLARE_GLOBAL_DATA_PTR;
24
Matt Porter1d0933e2013-10-07 15:53:02 +053025/* ti qpsi register bit masks */
26#define QSPI_TIMEOUT 2000000
Vignesh Ra6f56ad2016-07-25 15:45:45 +053027#define QSPI_FCLK 192000000
28#define QSPI_DRA7XX_FCLK 76800000
Vignesh R26036852016-09-07 15:18:22 +053029#define QSPI_WLEN_MAX_BITS 128
30#define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3)
31#define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
Matt Porter1d0933e2013-10-07 15:53:02 +053032/* clock control */
Jagan Teki847720c2015-10-23 01:39:20 +053033#define QSPI_CLK_EN BIT(31)
Matt Porter1d0933e2013-10-07 15:53:02 +053034#define QSPI_CLK_DIV_MAX 0xffff
35/* command */
36#define QSPI_EN_CS(n) (n << 28)
37#define QSPI_WLEN(n) ((n-1) << 19)
Jagan Teki847720c2015-10-23 01:39:20 +053038#define QSPI_3_PIN BIT(18)
39#define QSPI_RD_SNGL BIT(16)
Matt Porter1d0933e2013-10-07 15:53:02 +053040#define QSPI_WR_SNGL (2 << 16)
41#define QSPI_INVAL (4 << 16)
42#define QSPI_RD_QUAD (7 << 16)
43/* device control */
44#define QSPI_DD(m, n) (m << (3 + n*8))
45#define QSPI_CKPHA(n) (1 << (2 + n*8))
46#define QSPI_CSPOL(n) (1 << (1 + n*8))
47#define QSPI_CKPOL(n) (1 << (n*8))
48/* status */
Jagan Teki847720c2015-10-23 01:39:20 +053049#define QSPI_WC BIT(1)
50#define QSPI_BUSY BIT(0)
Matt Porter1d0933e2013-10-07 15:53:02 +053051#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
52#define QSPI_XFER_DONE QSPI_WC
53#define MM_SWITCH 0x01
Mugunthan V Nec712f42015-12-23 20:39:33 +053054#define MEM_CS(cs) ((cs + 1) << 8)
Praneeth Bajjuri8dfd6e22016-06-21 14:05:36 +053055#define MEM_CS_UNSELECT 0xfffff8ff
Sourav Poddar570533b2013-12-21 12:50:09 +053056#define MMAP_START_ADDR_DRA 0x5c000000
57#define MMAP_START_ADDR_AM43x 0x30000000
Matt Porter1d0933e2013-10-07 15:53:02 +053058#define CORE_CTRL_IO 0x4a002558
59
60#define QSPI_CMD_READ (0x3 << 0)
Mugunthan V N106f8132015-12-23 20:39:40 +053061#define QSPI_CMD_READ_DUAL (0x6b << 0)
Vignesh R74d49bf2015-11-23 17:43:36 +053062#define QSPI_CMD_READ_QUAD (0x6c << 0)
Matt Porter1d0933e2013-10-07 15:53:02 +053063#define QSPI_CMD_READ_FAST (0x0b << 0)
Vignesh R74d49bf2015-11-23 17:43:36 +053064#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)
Matt Porter1d0933e2013-10-07 15:53:02 +053065#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
66#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
67#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
Mugunthan V N106f8132015-12-23 20:39:40 +053068#define QSPI_SETUP0_READ_DUAL (0x1 << 12)
Matt Porter1d0933e2013-10-07 15:53:02 +053069#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
Vignesh R74d49bf2015-11-23 17:43:36 +053070#define QSPI_CMD_WRITE (0x12 << 16)
Matt Porter1d0933e2013-10-07 15:53:02 +053071#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
72
73/* ti qspi register set */
74struct ti_qspi_regs {
75 u32 pid;
76 u32 pad0[3];
77 u32 sysconfig;
78 u32 pad1[3];
79 u32 int_stat_raw;
80 u32 int_stat_en;
81 u32 int_en_set;
82 u32 int_en_ctlr;
83 u32 intc_eoi;
84 u32 pad2[3];
85 u32 clk_ctrl;
86 u32 dc;
87 u32 cmd;
88 u32 status;
89 u32 data;
90 u32 setup0;
91 u32 setup1;
92 u32 setup2;
93 u32 setup3;
94 u32 memswitch;
95 u32 data1;
96 u32 data2;
97 u32 data3;
98};
99
Mugunthan V N9c425582015-12-23 20:39:34 +0530100/* ti qspi priv */
101struct ti_qspi_priv {
Mugunthan V N106f8132015-12-23 20:39:40 +0530102#ifndef CONFIG_DM_SPI
Matt Porter1d0933e2013-10-07 15:53:02 +0530103 struct spi_slave slave;
Mugunthan V N106f8132015-12-23 20:39:40 +0530104#else
105 void *memory_map;
106 uint max_hz;
107 u32 num_cs;
108#endif
Matt Porter1d0933e2013-10-07 15:53:02 +0530109 struct ti_qspi_regs *base;
Mugunthan V N22309142015-12-23 20:39:35 +0530110 void *ctrl_mod_mmap;
Vignesh Ra6f56ad2016-07-25 15:45:45 +0530111 ulong fclk;
Matt Porter1d0933e2013-10-07 15:53:02 +0530112 unsigned int mode;
113 u32 cmd;
114 u32 dc;
115};
116
Mugunthan V N22309142015-12-23 20:39:35 +0530117static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
Matt Porter1d0933e2013-10-07 15:53:02 +0530118{
Matt Porter1d0933e2013-10-07 15:53:02 +0530119 uint clk_div;
120
Matt Porter1d0933e2013-10-07 15:53:02 +0530121 if (!hz)
122 clk_div = 0;
123 else
Vignesh R948b8bb2016-11-05 16:05:16 +0530124 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
125
126 /* truncate clk_div value to QSPI_CLK_DIV_MAX */
127 if (clk_div > QSPI_CLK_DIV_MAX)
128 clk_div = QSPI_CLK_DIV_MAX;
Matt Porter1d0933e2013-10-07 15:53:02 +0530129
Vignesh Rc595a282016-07-22 10:55:49 +0530130 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
131
Matt Porter1d0933e2013-10-07 15:53:02 +0530132 /* disable SCLK */
Mugunthan V N9c425582015-12-23 20:39:34 +0530133 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
134 &priv->base->clk_ctrl);
Vignesh R948b8bb2016-11-05 16:05:16 +0530135 /* enable SCLK and program the clk divider */
Mugunthan V N9c425582015-12-23 20:39:34 +0530136 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
Matt Porter1d0933e2013-10-07 15:53:02 +0530137}
138
Mugunthan V N22309142015-12-23 20:39:35 +0530139static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
Matt Porter1d0933e2013-10-07 15:53:02 +0530140{
Mugunthan V N9c425582015-12-23 20:39:34 +0530141 writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
Vignesh R857db482015-11-10 11:52:10 +0530142 /* dummy readl to ensure bus sync */
Mugunthan V N22309142015-12-23 20:39:35 +0530143 readl(&priv->base->cmd);
Matt Porter1d0933e2013-10-07 15:53:02 +0530144}
145
Mugunthan V N22309142015-12-23 20:39:35 +0530146static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
Matt Porter1d0933e2013-10-07 15:53:02 +0530147{
Mugunthan V N9c425582015-12-23 20:39:34 +0530148 priv->dc = 0;
Mugunthan V N22309142015-12-23 20:39:35 +0530149 if (mode & SPI_CPHA)
150 priv->dc |= QSPI_CKPHA(0);
151 if (mode & SPI_CPOL)
152 priv->dc |= QSPI_CKPOL(0);
153 if (mode & SPI_CS_HIGH)
154 priv->dc |= QSPI_CSPOL(0);
Matt Porter1d0933e2013-10-07 15:53:02 +0530155
156 return 0;
157}
158
Mugunthan V N22309142015-12-23 20:39:35 +0530159static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
Matt Porter1d0933e2013-10-07 15:53:02 +0530160{
Mugunthan V N22309142015-12-23 20:39:35 +0530161 writel(priv->dc, &priv->base->dc);
162 writel(0, &priv->base->cmd);
163 writel(0, &priv->base->data);
Matt Porter1d0933e2013-10-07 15:53:02 +0530164
Mugunthan V N22309142015-12-23 20:39:35 +0530165 priv->dc <<= cs * 8;
166 writel(priv->dc, &priv->base->dc);
Matt Porter1d0933e2013-10-07 15:53:02 +0530167
Mugunthan V N22309142015-12-23 20:39:35 +0530168 return 0;
169}
170
171static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
172{
Mugunthan V N9c425582015-12-23 20:39:34 +0530173 writel(0, &priv->base->dc);
174 writel(0, &priv->base->cmd);
175 writel(0, &priv->base->data);
Matt Porter1d0933e2013-10-07 15:53:02 +0530176}
177
Mugunthan V N22309142015-12-23 20:39:35 +0530178static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
Matt Porter1d0933e2013-10-07 15:53:02 +0530179{
Mugunthan V N22309142015-12-23 20:39:35 +0530180 u32 val;
181
182 val = readl(ctrl_mod_mmap);
183 if (enable)
184 val |= MEM_CS(cs);
185 else
186 val &= MEM_CS_UNSELECT;
187 writel(val, ctrl_mod_mmap);
188}
189
190static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
191 const void *dout, void *din, unsigned long flags,
192 u32 cs)
193{
Matt Porter1d0933e2013-10-07 15:53:02 +0530194 uint words = bitlen >> 3; /* fixed 8-bit word length */
195 const uchar *txp = dout;
196 uchar *rxp = din;
197 uint status;
Sourav Poddar570533b2013-12-21 12:50:09 +0530198 int timeout;
199
Matt Porter1d0933e2013-10-07 15:53:02 +0530200 /* Setup mmap flags */
201 if (flags & SPI_XFER_MMAP) {
Mugunthan V N9c425582015-12-23 20:39:34 +0530202 writel(MM_SWITCH, &priv->base->memswitch);
Mugunthan V N22309142015-12-23 20:39:35 +0530203 if (priv->ctrl_mod_mmap)
204 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
Matt Porter1d0933e2013-10-07 15:53:02 +0530205 return 0;
206 } else if (flags & SPI_XFER_MMAP_END) {
Mugunthan V N9c425582015-12-23 20:39:34 +0530207 writel(~MM_SWITCH, &priv->base->memswitch);
Mugunthan V N22309142015-12-23 20:39:35 +0530208 if (priv->ctrl_mod_mmap)
209 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
Matt Porter1d0933e2013-10-07 15:53:02 +0530210 return 0;
211 }
212
213 if (bitlen == 0)
214 return -1;
215
216 if (bitlen % 8) {
217 debug("spi_xfer: Non byte aligned SPI transfer\n");
218 return -1;
219 }
220
221 /* Setup command reg */
Mugunthan V N9c425582015-12-23 20:39:34 +0530222 priv->cmd = 0;
223 priv->cmd |= QSPI_WLEN(8);
Mugunthan V N22309142015-12-23 20:39:35 +0530224 priv->cmd |= QSPI_EN_CS(cs);
Mugunthan V N9c425582015-12-23 20:39:34 +0530225 if (priv->mode & SPI_3WIRE)
226 priv->cmd |= QSPI_3_PIN;
227 priv->cmd |= 0xfff;
Matt Porter1d0933e2013-10-07 15:53:02 +0530228
Vignesh R26036852016-09-07 15:18:22 +0530229 while (words) {
230 u8 xfer_len = 0;
231
Matt Porter1d0933e2013-10-07 15:53:02 +0530232 if (txp) {
Vignesh R26036852016-09-07 15:18:22 +0530233 u32 cmd = priv->cmd;
234
235 if (words >= QSPI_WLEN_MAX_BYTES) {
236 u32 *txbuf = (u32 *)txp;
237 u32 data;
238
239 data = cpu_to_be32(*txbuf++);
240 writel(data, &priv->base->data3);
241 data = cpu_to_be32(*txbuf++);
242 writel(data, &priv->base->data2);
243 data = cpu_to_be32(*txbuf++);
244 writel(data, &priv->base->data1);
245 data = cpu_to_be32(*txbuf++);
246 writel(data, &priv->base->data);
247 cmd &= ~QSPI_WLEN_MASK;
248 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
249 xfer_len = QSPI_WLEN_MAX_BYTES;
250 } else {
251 writeb(*txp, &priv->base->data);
252 xfer_len = 1;
253 }
254 debug("tx cmd %08x dc %08x\n",
255 cmd | QSPI_WR_SNGL, priv->dc);
256 writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
Mugunthan V N9c425582015-12-23 20:39:34 +0530257 status = readl(&priv->base->status);
Matt Porter1d0933e2013-10-07 15:53:02 +0530258 timeout = QSPI_TIMEOUT;
259 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
260 if (--timeout < 0) {
261 printf("spi_xfer: TX timeout!\n");
262 return -1;
263 }
Mugunthan V N9c425582015-12-23 20:39:34 +0530264 status = readl(&priv->base->status);
Matt Porter1d0933e2013-10-07 15:53:02 +0530265 }
Vignesh R26036852016-09-07 15:18:22 +0530266 txp += xfer_len;
Matt Porter1d0933e2013-10-07 15:53:02 +0530267 debug("tx done, status %08x\n", status);
268 }
269 if (rxp) {
Matt Porter1d0933e2013-10-07 15:53:02 +0530270 debug("rx cmd %08x dc %08x\n",
Vignesh R69eeefa2016-07-22 10:55:48 +0530271 ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
Vignesh R69eeefa2016-07-22 10:55:48 +0530272 writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
Mugunthan V N9c425582015-12-23 20:39:34 +0530273 status = readl(&priv->base->status);
Matt Porter1d0933e2013-10-07 15:53:02 +0530274 timeout = QSPI_TIMEOUT;
275 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
276 if (--timeout < 0) {
277 printf("spi_xfer: RX timeout!\n");
278 return -1;
279 }
Mugunthan V N9c425582015-12-23 20:39:34 +0530280 status = readl(&priv->base->status);
Matt Porter1d0933e2013-10-07 15:53:02 +0530281 }
Mugunthan V N9c425582015-12-23 20:39:34 +0530282 *rxp++ = readl(&priv->base->data);
Vignesh R26036852016-09-07 15:18:22 +0530283 xfer_len = 1;
Matt Porter1d0933e2013-10-07 15:53:02 +0530284 debug("rx done, status %08x, read %02x\n",
285 status, *(rxp-1));
286 }
Vignesh R26036852016-09-07 15:18:22 +0530287 words -= xfer_len;
Matt Porter1d0933e2013-10-07 15:53:02 +0530288 }
289
290 /* Terminate frame */
291 if (flags & SPI_XFER_END)
Mugunthan V N22309142015-12-23 20:39:35 +0530292 ti_qspi_cs_deactivate(priv);
Matt Porter1d0933e2013-10-07 15:53:02 +0530293
294 return 0;
295}
Vignesh R8ddd9c42015-08-17 15:20:13 +0530296
297/* TODO: control from sf layer to here through dm-spi */
Mugunthan V N518b0af2016-02-15 15:31:40 +0530298#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
Vignesh R8ddd9c42015-08-17 15:20:13 +0530299void spi_flash_copy_mmap(void *data, void *offset, size_t len)
300{
301 unsigned int addr = (unsigned int) (data);
302 unsigned int edma_slot_num = 1;
303
304 /* Invalidate the area, so no writeback into the RAM races with DMA */
305 invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
306
307 /* enable edma3 clocks */
308 enable_edma3_clocks();
309
310 /* Call edma3 api to do actual DMA transfer */
311 edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
312
313 /* disable edma3 clocks */
314 disable_edma3_clocks();
315
316 *((unsigned int *)offset) += len;
317}
318#endif
Mugunthan V N22309142015-12-23 20:39:35 +0530319
Mugunthan V N106f8132015-12-23 20:39:40 +0530320#ifndef CONFIG_DM_SPI
321
Mugunthan V N22309142015-12-23 20:39:35 +0530322static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
323{
324 return container_of(slave, struct ti_qspi_priv, slave);
325}
326
327int spi_cs_is_valid(unsigned int bus, unsigned int cs)
328{
329 return 1;
330}
331
332void spi_cs_activate(struct spi_slave *slave)
333{
334 /* CS handled in xfer */
335 return;
336}
337
338void spi_cs_deactivate(struct spi_slave *slave)
339{
340 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
341 ti_qspi_cs_deactivate(priv);
342}
343
344void spi_init(void)
345{
346 /* nothing to do */
347}
348
349static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
350{
351 u32 memval = 0;
352
353#ifdef CONFIG_QSPI_QUAD_SUPPORT
354 struct spi_slave *slave = &priv->slave;
355 memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
356 QSPI_SETUP0_NUM_D_BYTES_8_BITS |
357 QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
358 QSPI_NUM_DUMMY_BITS);
Jagan Teki08fe9c22016-08-08 17:12:12 +0530359 slave->mode |= SPI_RX_QUAD;
Mugunthan V N22309142015-12-23 20:39:35 +0530360#else
361 memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
362 QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
363 QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
364 QSPI_NUM_DUMMY_BITS;
365#endif
366
367 writel(memval, &priv->base->setup0);
368}
369
370struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
371 unsigned int max_hz, unsigned int mode)
372{
373 struct ti_qspi_priv *priv;
374
375#ifdef CONFIG_AM43XX
376 gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
377 gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
378#endif
379
380 priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
381 if (!priv) {
382 printf("SPI_error: Fail to allocate ti_qspi_priv\n");
383 return NULL;
384 }
385
386 priv->base = (struct ti_qspi_regs *)QSPI_BASE;
387 priv->mode = mode;
Nishanth Menon3891a542016-11-29 15:22:00 +0530388#if defined(CONFIG_DRA7XX)
Mugunthan V N22309142015-12-23 20:39:35 +0530389 priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
390 priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
Vignesh Ra6f56ad2016-07-25 15:45:45 +0530391 priv->fclk = QSPI_DRA7XX_FCLK;
Mugunthan V N22309142015-12-23 20:39:35 +0530392#else
393 priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
Vignesh Ra6f56ad2016-07-25 15:45:45 +0530394 priv->fclk = QSPI_FCLK;
Mugunthan V N22309142015-12-23 20:39:35 +0530395#endif
396
397 ti_spi_set_speed(priv, max_hz);
398
399#ifdef CONFIG_TI_SPI_MMAP
400 ti_spi_setup_spi_register(priv);
401#endif
402
403 return &priv->slave;
404}
405
406void spi_free_slave(struct spi_slave *slave)
407{
408 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
409 free(priv);
410}
411
412int spi_claim_bus(struct spi_slave *slave)
413{
414 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
415
416 debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
417 __ti_qspi_set_mode(priv, priv->mode);
418 return __ti_qspi_claim_bus(priv, priv->slave.cs);
419}
420void spi_release_bus(struct spi_slave *slave)
421{
422 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
423
424 debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
425 __ti_qspi_release_bus(priv);
426}
427
428int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
429 void *din, unsigned long flags)
430{
431 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
432
433 debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
434 priv->slave.bus, priv->slave.cs, bitlen, flags);
435 return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
436}
Mugunthan V N106f8132015-12-23 20:39:40 +0530437
438#else /* CONFIG_DM_SPI */
439
440static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
441 struct spi_slave *slave,
442 bool enable)
443{
444 u32 memval;
Jagan Teki08fe9c22016-08-08 17:12:12 +0530445 u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL);
Mugunthan V N106f8132015-12-23 20:39:40 +0530446
447 if (!enable) {
448 writel(0, &priv->base->setup0);
449 return;
450 }
451
452 memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
453
454 switch (mode) {
455 case SPI_RX_QUAD:
456 memval |= QSPI_CMD_READ_QUAD;
457 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
458 memval |= QSPI_SETUP0_READ_QUAD;
Jagan Teki08fe9c22016-08-08 17:12:12 +0530459 slave->mode |= SPI_RX_QUAD;
Mugunthan V N106f8132015-12-23 20:39:40 +0530460 break;
461 case SPI_RX_DUAL:
462 memval |= QSPI_CMD_READ_DUAL;
463 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
464 memval |= QSPI_SETUP0_READ_DUAL;
465 break;
466 default:
467 memval |= QSPI_CMD_READ;
468 memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
469 memval |= QSPI_SETUP0_READ_NORMAL;
470 break;
471 }
472
473 writel(memval, &priv->base->setup0);
474}
475
476
477static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
478{
479 struct ti_qspi_priv *priv = dev_get_priv(bus);
480
481 ti_spi_set_speed(priv, max_hz);
482
483 return 0;
484}
485
486static int ti_qspi_set_mode(struct udevice *bus, uint mode)
487{
488 struct ti_qspi_priv *priv = dev_get_priv(bus);
489 return __ti_qspi_set_mode(priv, mode);
490}
491
492static int ti_qspi_claim_bus(struct udevice *dev)
493{
494 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
495 struct spi_slave *slave = dev_get_parent_priv(dev);
496 struct ti_qspi_priv *priv;
497 struct udevice *bus;
498
499 bus = dev->parent;
500 priv = dev_get_priv(bus);
501
502 if (slave_plat->cs > priv->num_cs) {
503 debug("invalid qspi chip select\n");
504 return -EINVAL;
505 }
506
507 __ti_qspi_setup_memorymap(priv, slave, true);
508
509 return __ti_qspi_claim_bus(priv, slave_plat->cs);
510}
511
512static int ti_qspi_release_bus(struct udevice *dev)
513{
514 struct spi_slave *slave = dev_get_parent_priv(dev);
515 struct ti_qspi_priv *priv;
516 struct udevice *bus;
517
518 bus = dev->parent;
519 priv = dev_get_priv(bus);
520
521 __ti_qspi_setup_memorymap(priv, slave, false);
522 __ti_qspi_release_bus(priv);
523
524 return 0;
525}
526
527static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
528 const void *dout, void *din, unsigned long flags)
529{
530 struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
531 struct ti_qspi_priv *priv;
532 struct udevice *bus;
533
534 bus = dev->parent;
535 priv = dev_get_priv(bus);
536
537 if (slave->cs > priv->num_cs) {
538 debug("invalid qspi chip select\n");
539 return -EINVAL;
540 }
541
542 return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
543}
544
545static int ti_qspi_probe(struct udevice *bus)
546{
Vignesh Ra6f56ad2016-07-25 15:45:45 +0530547 struct ti_qspi_priv *priv = dev_get_priv(bus);
548
549 priv->fclk = dev_get_driver_data(bus);
550
Mugunthan V N106f8132015-12-23 20:39:40 +0530551 return 0;
552}
553
Jean-Jacques Hiblotb06a3812017-02-13 16:17:49 +0100554static void *map_syscon_chipselects(struct udevice *bus)
555{
556#if CONFIG_IS_ENABLED(SYSCON)
557 struct udevice *syscon;
558 struct regmap *regmap;
559 const fdt32_t *cell;
560 int len, err;
561
562 err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
563 "syscon-chipselects", &syscon);
564 if (err) {
565 debug("%s: unable to find syscon device (%d)\n", __func__,
566 err);
567 return NULL;
568 }
569
570 regmap = syscon_get_regmap(syscon);
571 if (IS_ERR(regmap)) {
572 debug("%s: unable to find regmap (%ld)\n", __func__,
573 PTR_ERR(regmap));
574 return NULL;
575 }
576
Simon Glassda409cc2017-05-17 17:18:09 -0600577 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
578 "syscon-chipselects", &len);
Jean-Jacques Hiblotb06a3812017-02-13 16:17:49 +0100579 if (len < 2*sizeof(fdt32_t)) {
580 debug("%s: offset not available\n", __func__);
581 return NULL;
582 }
583
584 return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
585#else
586 fdt_addr_t addr;
Simon Glassa821c4a2017-05-17 17:18:05 -0600587 addr = devfdt_get_addr_index(bus, 2);
Jean-Jacques Hiblotb06a3812017-02-13 16:17:49 +0100588 return (addr == FDT_ADDR_T_NONE) ? NULL :
589 map_physmem(addr, 0, MAP_NOCACHE);
590#endif
591}
592
Mugunthan V N106f8132015-12-23 20:39:40 +0530593static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
594{
595 struct ti_qspi_priv *priv = dev_get_priv(bus);
596 const void *blob = gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -0700597 int node = dev_of_offset(bus);
Mugunthan V N106f8132015-12-23 20:39:40 +0530598
Jean-Jacques Hiblotb06a3812017-02-13 16:17:49 +0100599 priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
Simon Glassa821c4a2017-05-17 17:18:05 -0600600 priv->base = map_physmem(devfdt_get_addr(bus),
601 sizeof(struct ti_qspi_regs), MAP_NOCACHE);
602 priv->memory_map = map_physmem(devfdt_get_addr_index(bus, 1), 0,
Lokesh Vutlae6601df2016-03-05 16:43:06 +0530603 MAP_NOCACHE);
Mugunthan V N106f8132015-12-23 20:39:40 +0530604
605 priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
606 if (priv->max_hz < 0) {
607 debug("Error: Max frequency missing\n");
608 return -ENODEV;
609 }
610 priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
611
612 debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
613 (int)priv->base, priv->max_hz);
614
615 return 0;
616}
617
618static int ti_qspi_child_pre_probe(struct udevice *dev)
619{
620 struct spi_slave *slave = dev_get_parent_priv(dev);
621 struct udevice *bus = dev_get_parent(dev);
622 struct ti_qspi_priv *priv = dev_get_priv(bus);
623
624 slave->memory_map = priv->memory_map;
625 return 0;
626}
627
628static const struct dm_spi_ops ti_qspi_ops = {
629 .claim_bus = ti_qspi_claim_bus,
630 .release_bus = ti_qspi_release_bus,
631 .xfer = ti_qspi_xfer,
632 .set_speed = ti_qspi_set_speed,
633 .set_mode = ti_qspi_set_mode,
634};
635
636static const struct udevice_id ti_qspi_ids[] = {
Vignesh Ra6f56ad2016-07-25 15:45:45 +0530637 { .compatible = "ti,dra7xxx-qspi", .data = QSPI_DRA7XX_FCLK},
638 { .compatible = "ti,am4372-qspi", .data = QSPI_FCLK},
Mugunthan V N106f8132015-12-23 20:39:40 +0530639 { }
640};
641
642U_BOOT_DRIVER(ti_qspi) = {
643 .name = "ti_qspi",
644 .id = UCLASS_SPI,
645 .of_match = ti_qspi_ids,
646 .ops = &ti_qspi_ops,
647 .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
648 .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
649 .probe = ti_qspi_probe,
650 .child_pre_probe = ti_qspi_child_pre_probe,
651};
652#endif /* CONFIG_DM_SPI */