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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Heiko Schocherb89ac722013-12-02 07:47:23 +01002/*
3 * Common board functions for siemens AT91SAM9G45 based boards
4 * (C) Copyright 2013 Siemens AG
5 *
6 * Based on:
7 * U-Boot file: include/configs/at91sam9m10g45ek.h
8 * (C) Copyright 2007-2008
9 * Stelian Pop <stelian@popies.net>
10 * Lead Tech Design <www.leadtechdesign.com>
Heiko Schocherb89ac722013-12-02 07:47:23 +010011 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16#include <asm/hardware.h>
Heiko Schocherfd45a0d2015-08-21 11:28:19 +020017#include <linux/sizes.h>
Heiko Schocherb89ac722013-12-02 07:47:23 +010018
Heiko Schocherb89ac722013-12-02 07:47:23 +010019/*
Simon Glass98463902022-10-20 18:22:39 -060020 * Warning: changing CONFIG_TEXT_BASE requires
Heiko Schocherb89ac722013-12-02 07:47:23 +010021 * adapting the initial boot program.
22 * Since the linker has to swallow that define, we must use a pure
23 * hex number here!
24 */
25
Heiko Schocherb89ac722013-12-02 07:47:23 +010026/* ARM asynchronous clock */
Tom Rini65cc0e22022-11-16 13:10:41 -050027#define CFG_SYS_AT91_SLOW_CLOCK 32768
28#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
Heiko Schocherb89ac722013-12-02 07:47:23 +010029
Heiko Schocherb89ac722013-12-02 07:47:23 +010030/* serial console */
Tom Rini805482d2022-12-04 10:14:02 -050031#define CFG_USART_BASE ATMEL_BASE_DBGU
Tom Rini61693ac2022-12-04 10:14:03 -050032#define CFG_USART_ID ATMEL_ID_SYS
Heiko Schocherb89ac722013-12-02 07:47:23 +010033
Heiko Schocherb89ac722013-12-02 07:47:23 +010034/* SDRAM */
Tom Riniaa6e94d2022-11-16 13:10:37 -050035#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6
36#define CFG_SYS_SDRAM_SIZE 0x08000000
Heiko Schocherb89ac722013-12-02 07:47:23 +010037
Heiko Schocherb89ac722013-12-02 07:47:23 +010038/* NAND flash */
39#ifdef CONFIG_CMD_NAND
Tom Rini4e590942022-11-12 17:36:51 -050040#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
Heiko Schocherb89ac722013-12-02 07:47:23 +010041/* our ALE is AD21 */
Tom Rini4e590942022-11-12 17:36:51 -050042#define CFG_SYS_NAND_MASK_ALE (1 << 21)
Heiko Schocherb89ac722013-12-02 07:47:23 +010043/* our CLE is AD22 */
Tom Rini4e590942022-11-12 17:36:51 -050044#define CFG_SYS_NAND_MASK_CLE (1 << 22)
45#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
46#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC8
Heiko Schocherb89ac722013-12-02 07:47:23 +010047#endif
48
Heiko Schochere11793b2015-08-21 11:28:20 +020049/* DFU class support */
Heiko Schochere11793b2015-08-21 11:28:20 +020050#define DFU_MANIFEST_POLL_TIMEOUT 25000
51
Heiko Schocherb89ac722013-12-02 07:47:23 +010052/* bootstrap + u-boot + env in nandflash */
Heiko Schocherb89ac722013-12-02 07:47:23 +010053
Heiko Schocher5b15fd92014-10-31 08:31:06 +010054/* Defines for SPL */
Heiko Schocher5b15fd92014-10-31 08:31:06 +010055
Tom Rini4e590942022-11-12 17:36:51 -050056#define CFG_SYS_NAND_U_BOOT_SIZE 0x80000
57#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
58#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
Heiko Schocher5b15fd92014-10-31 08:31:06 +010059
Tom Rini4e590942022-11-12 17:36:51 -050060#define CFG_SYS_NAND_ECCSIZE 256
61#define CFG_SYS_NAND_ECCBYTES 3
62#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
Heiko Schocher5b15fd92014-10-31 08:31:06 +010063 48, 49, 50, 51, 52, 53, 54, 55, \
64 56, 57, 58, 59, 60, 61, 62, 63, }
65
Tom Rini65cc0e22022-11-16 13:10:41 -050066#define CFG_SYS_MASTER_CLOCK 132096000
Heiko Schocher5b15fd92014-10-31 08:31:06 +010067#define AT91_PLL_LOCK_TIMEOUT 1000000
Tom Rini65cc0e22022-11-16 13:10:41 -050068#define CFG_SYS_AT91_PLLA 0x20c73f03
69#define CFG_SYS_MCKR 0x1301
70#define CFG_SYS_MCKR_CSS 0x1302
Heiko Schocher5b15fd92014-10-31 08:31:06 +010071
Heiko Schocherb89ac722013-12-02 07:47:23 +010072#endif