Tom Rix | cd78263 | 2009-06-28 12:52:29 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2009 Wind River Systems, Inc. |
| 3 | * Tom Rix <Tom.Rix at windriver.com> |
| 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Tom Rix | cd78263 | 2009-06-28 12:52:29 -0500 | [diff] [blame] | 6 | * |
Tom Rix | 2c15513 | 2009-06-28 12:52:30 -0500 | [diff] [blame] | 7 | * twl4030_power_reset_init is derived from code on omapzoom, |
| 8 | * git://git.omapzoom.com/repo/u-boot.git |
Tom Rix | cd78263 | 2009-06-28 12:52:29 -0500 | [diff] [blame] | 9 | * |
| 10 | * Copyright (C) 2007-2009 Texas Instruments, Inc. |
Tom Rix | 2c15513 | 2009-06-28 12:52:30 -0500 | [diff] [blame] | 11 | * |
| 12 | * twl4030_power_init is from cpu/omap3/common.c, power_init_r |
| 13 | * |
| 14 | * (C) Copyright 2004-2008 |
| 15 | * Texas Instruments, <www.ti.com> |
| 16 | * |
| 17 | * Author : |
| 18 | * Sunil Kumar <sunilsaini05 at gmail.com> |
| 19 | * Shashi Ranjan <shashiranjanmca05 at gmail.com> |
| 20 | * |
| 21 | * Derived from Beagle Board and 3430 SDP code by |
| 22 | * Richard Woodruff <r-woodruff2 at ti.com> |
| 23 | * Syed Mohammed Khasim <khasim at ti.com> |
Tom Rix | cd78263 | 2009-06-28 12:52:29 -0500 | [diff] [blame] | 24 | */ |
| 25 | |
| 26 | #include <twl4030.h> |
| 27 | |
| 28 | /* |
| 29 | * Power Reset |
| 30 | */ |
| 31 | void twl4030_power_reset_init(void) |
| 32 | { |
| 33 | u8 val = 0; |
Nishanth Menon | b29c2f0 | 2013-03-26 05:20:50 +0000 | [diff] [blame] | 34 | if (twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, |
| 35 | TWL4030_PM_MASTER_P1_SW_EVENTS, &val)) { |
Tom Rix | cd78263 | 2009-06-28 12:52:29 -0500 | [diff] [blame] | 36 | printf("Error:TWL4030: failed to read the power register\n"); |
| 37 | printf("Could not initialize hardware reset\n"); |
| 38 | } else { |
| 39 | val |= TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON; |
Nishanth Menon | 0208aaf | 2013-03-26 05:20:49 +0000 | [diff] [blame] | 40 | if (twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, |
| 41 | TWL4030_PM_MASTER_P1_SW_EVENTS, val)) { |
Tom Rix | cd78263 | 2009-06-28 12:52:29 -0500 | [diff] [blame] | 42 | printf("Error:TWL4030: failed to write the power register\n"); |
| 43 | printf("Could not initialize hardware reset\n"); |
| 44 | } |
| 45 | } |
| 46 | } |
| 47 | |
Tom Rix | 2c15513 | 2009-06-28 12:52:30 -0500 | [diff] [blame] | 48 | /* |
Steve Sakoman | 5a0a82f | 2010-08-10 12:58:39 -0700 | [diff] [blame] | 49 | * Set Device Group and Voltage |
Tom Rix | 2c15513 | 2009-06-28 12:52:30 -0500 | [diff] [blame] | 50 | */ |
Steve Sakoman | 5a0a82f | 2010-08-10 12:58:39 -0700 | [diff] [blame] | 51 | void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val, |
| 52 | u8 dev_grp, u8 dev_grp_sel) |
| 53 | { |
Grazvydas Ignotas | 61712bc | 2012-03-19 03:37:40 +0000 | [diff] [blame] | 54 | int ret; |
Steve Sakoman | 5a0a82f | 2010-08-10 12:58:39 -0700 | [diff] [blame] | 55 | |
| 56 | /* Select the Voltage */ |
Nishanth Menon | 0208aaf | 2013-03-26 05:20:49 +0000 | [diff] [blame] | 57 | ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_reg, |
| 58 | vsel_val); |
Grazvydas Ignotas | 61712bc | 2012-03-19 03:37:40 +0000 | [diff] [blame] | 59 | if (ret != 0) { |
Peter Meerwald | dfe3610 | 2012-11-19 23:13:04 +0000 | [diff] [blame] | 60 | printf("Could not write vsel to reg %02x (%d)\n", |
Grazvydas Ignotas | 61712bc | 2012-03-19 03:37:40 +0000 | [diff] [blame] | 61 | vsel_reg, ret); |
| 62 | return; |
| 63 | } |
| 64 | |
| 65 | /* Select the Device Group (enable the supply if dev_grp_sel != 0) */ |
Nishanth Menon | 0208aaf | 2013-03-26 05:20:49 +0000 | [diff] [blame] | 66 | ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp, |
| 67 | dev_grp_sel); |
Grazvydas Ignotas | 61712bc | 2012-03-19 03:37:40 +0000 | [diff] [blame] | 68 | if (ret != 0) |
Peter Meerwald | dfe3610 | 2012-11-19 23:13:04 +0000 | [diff] [blame] | 69 | printf("Could not write grp_sel to reg %02x (%d)\n", |
Grazvydas Ignotas | 61712bc | 2012-03-19 03:37:40 +0000 | [diff] [blame] | 70 | dev_grp, ret); |
Steve Sakoman | 5a0a82f | 2010-08-10 12:58:39 -0700 | [diff] [blame] | 71 | } |
Tom Rix | 2c15513 | 2009-06-28 12:52:30 -0500 | [diff] [blame] | 72 | |
| 73 | void twl4030_power_init(void) |
| 74 | { |
Tom Rix | 2c15513 | 2009-06-28 12:52:30 -0500 | [diff] [blame] | 75 | /* set VAUX3 to 2.8V */ |
Steve Sakoman | 5a0a82f | 2010-08-10 12:58:39 -0700 | [diff] [blame] | 76 | twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX3_DEDICATED, |
| 77 | TWL4030_PM_RECEIVER_VAUX3_VSEL_28, |
| 78 | TWL4030_PM_RECEIVER_VAUX3_DEV_GRP, |
| 79 | TWL4030_PM_RECEIVER_DEV_GRP_P1); |
Tom Rix | 2c15513 | 2009-06-28 12:52:30 -0500 | [diff] [blame] | 80 | |
| 81 | /* set VPLL2 to 1.8V */ |
Steve Sakoman | 5a0a82f | 2010-08-10 12:58:39 -0700 | [diff] [blame] | 82 | twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VPLL2_DEDICATED, |
| 83 | TWL4030_PM_RECEIVER_VPLL2_VSEL_18, |
| 84 | TWL4030_PM_RECEIVER_VPLL2_DEV_GRP, |
| 85 | TWL4030_PM_RECEIVER_DEV_GRP_ALL); |
Tom Rix | 2c15513 | 2009-06-28 12:52:30 -0500 | [diff] [blame] | 86 | |
| 87 | /* set VDAC to 1.8V */ |
Steve Sakoman | 5a0a82f | 2010-08-10 12:58:39 -0700 | [diff] [blame] | 88 | twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VDAC_DEDICATED, |
| 89 | TWL4030_PM_RECEIVER_VDAC_VSEL_18, |
| 90 | TWL4030_PM_RECEIVER_VDAC_DEV_GRP, |
| 91 | TWL4030_PM_RECEIVER_DEV_GRP_P1); |
Tom Rix | 2c15513 | 2009-06-28 12:52:30 -0500 | [diff] [blame] | 92 | } |
| 93 | |
Tom Rix | fccc0fc | 2009-06-28 12:52:31 -0500 | [diff] [blame] | 94 | void twl4030_power_mmc_init(void) |
| 95 | { |
Ash Charles | 528cdca | 2011-09-28 06:47:16 +0000 | [diff] [blame] | 96 | /* Set VMMC1 to 3.15 Volts */ |
Steve Sakoman | 5a0a82f | 2010-08-10 12:58:39 -0700 | [diff] [blame] | 97 | twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED, |
Ash Charles | 528cdca | 2011-09-28 06:47:16 +0000 | [diff] [blame] | 98 | TWL4030_PM_RECEIVER_VMMC1_VSEL_32, |
Steve Sakoman | 5a0a82f | 2010-08-10 12:58:39 -0700 | [diff] [blame] | 99 | TWL4030_PM_RECEIVER_VMMC1_DEV_GRP, |
| 100 | TWL4030_PM_RECEIVER_DEV_GRP_P1); |
Tom Rix | fccc0fc | 2009-06-28 12:52:31 -0500 | [diff] [blame] | 101 | } |