Fabio Estevam | 3a21773 | 2014-01-03 15:55:58 -0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Boundary Devices |
| 3 | * Copyright (C) 2013 SolidRun ltd. |
| 4 | * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | /* |
| 10 | * DDR3 settings |
| 11 | * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), |
| 12 | * memory bus width: 64 bits x16/x32/x64 |
| 13 | * MX6DL ddr is limited to 800 MHz(400 MHz clock) |
| 14 | * memory bus width: 64 bits x16/x32/x64 |
| 15 | * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) |
| 16 | * memory bus width: 32 bits x16/x32 |
| 17 | */ |
| 18 | /* DDR IO TYPE */ |
| 19 | DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000 |
| 20 | DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 |
| 21 | /* Clock */ |
| 22 | DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028 |
| 23 | DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028 |
| 24 | /* Address */ |
| 25 | DATA 4, MX6_IOM_DRAM_CAS, 0x00000010 |
| 26 | DATA 4, MX6_IOM_DRAM_RAS, 0x00000010 |
| 27 | DATA 4, MX6_IOM_GRP_ADDDS, 0x00000010 |
| 28 | /* Control */ |
| 29 | DATA 4, MX6_IOM_DRAM_RESET, 0x00000010 |
| 30 | DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 |
| 31 | DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 |
| 32 | DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 |
| 33 | DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000010 |
| 34 | DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000010 |
| 35 | DATA 4, MX6_IOM_GRP_CTLDS, 0x00000010 |
| 36 | |
| 37 | /* |
| 38 | * Data Strobe: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DDR_INPUT=0, CMOS, |
| 39 | * CMOS mode saves power, but have less timing margin in case of DDR |
| 40 | * timing issue on your board you can try DDR_MODE: [= 0x00020000] |
| 41 | */ |
| 42 | DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 |
| 43 | |
| 44 | DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028 |
| 45 | DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028 |
| 46 | DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028 |
| 47 | DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028 |
| 48 | DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000 |
| 49 | DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000 |
| 50 | DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000 |
| 51 | DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000 |
| 52 | |
| 53 | /* |
| 54 | * DATA:IOMUXC_SW_PAD_CTL_GRP_DDRMODE - DDR_INPUT=0, CMOS, |
| 55 | * CMOS mode saves power, but have less timing margin in case of DDR |
| 56 | * timing issue on your board you can try DDR_MODE: [= 0x00020000] |
| 57 | */ |
| 58 | DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 |
| 59 | |
| 60 | DATA 4, MX6_IOM_GRP_B0DS, 0x00000028 |
| 61 | DATA 4, MX6_IOM_GRP_B1DS, 0x00000028 |
| 62 | DATA 4, MX6_IOM_GRP_B2DS, 0x00000028 |
| 63 | DATA 4, MX6_IOM_GRP_B3DS, 0x00000028 |
| 64 | DATA 4, MX6_IOM_GRP_B4DS, 0x00000000 |
| 65 | DATA 4, MX6_IOM_GRP_B5DS, 0x00000000 |
| 66 | DATA 4, MX6_IOM_GRP_B6DS, 0x00000000 |
| 67 | DATA 4, MX6_IOM_GRP_B7DS, 0x00000000 |
| 68 | |
| 69 | DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028 |
| 70 | DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028 |
| 71 | DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028 |
| 72 | DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028 |
| 73 | DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000 |
| 74 | DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000 |
| 75 | DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000 |
| 76 | DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000 |