| Wu, Josh | bdfd59a | 2012-08-23 00:05:36 +0000 | [diff] [blame] | 1 | How to enable PMECC(Programmable Multibit ECC) for nand on Atmel SoCs |
| 2 | ----------------------------------------------------------- |
| 3 | 2012-08-22 Josh Wu <josh.wu@atmel.com> |
| 4 | |
| 5 | The Programmable Multibit ECC (PMECC) controller is a programmable binary |
| 6 | BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. This controller |
| 7 | can be used to support both SLC and MLC NAND Flash devices. It supports to |
| 8 | generate ECC to correct 2, 4, 8, 12 or 24 bits of error per sector (512 or |
| 9 | 1024 bytes) of data. |
| 10 | |
| 11 | Following Atmel AT91 products support PMECC. |
| 12 | - AT91SAM9X25, X35, G25, G15, G35 (tested) |
| 13 | - AT91SAM9N12 (not tested, Should work) |
| 14 | |
| 15 | As soon as your nand flash software ECC works, you can enable PMECC. |
| 16 | |
| 17 | To use PMECC in this driver, the user needs to set: |
| 18 | 1. the PMECC correction error bits capability: CONFIG_PMECC_CAP. |
| 19 | It can be 2, 4, 8, 12 or 24. |
| 20 | 2. The PMECC sector size: CONFIG_PMECC_SECTOR_SIZE. |
| 21 | It only can be 512 or 1024. |
| Wu, Josh | bdfd59a | 2012-08-23 00:05:36 +0000 | [diff] [blame] | 22 | |
| 23 | Take AT91SAM9X5EK as an example, the board definition file likes: |
| 24 | |
| 25 | /* PMECC & PMERRLOC */ |
| 26 | #define CONFIG_ATMEL_NAND_HWECC 1 |
| 27 | #define CONFIG_ATMEL_NAND_HW_PMECC 1 |
| 28 | #define CONFIG_PMECC_CAP 2 |
| 29 | #define CONFIG_PMECC_SECTOR_SIZE 512 |
| Andreas Bießmann | 5c390a5 | 2014-05-19 14:23:40 +0200 | [diff] [blame] | 30 | |
| 31 | How to enable PMECC header for direct programmable boot.bin |
| 32 | ----------------------------------------------------------- |
| 33 | 2014-05-19 Andreas Bießmann <andreas.devel@googlemail.com> |
| 34 | |
| 35 | The usual way to program SPL into NAND flash is to use the SAM-BA Atmel tool. |
| 36 | This however is often not usable when doing field updates. To be able to |
| 37 | program a SPL binary into NAND flash we need to add the PMECC header to the |
| 38 | binary before. Chapter '12.4.4.1 NAND Flash Boot: NAND Flash Detection' in |
| 39 | sama5d3 SoC spec (as of 03. April 2014) defines how this PMECC header has to |
| 40 | look like. In order to do so we have a new image type added to mkimage to |
| 41 | generate this PMECC header and integrated this into the build process of SPL. |
| 42 | |
| 43 | To enable the generation of atmel PMECC header for SPL one need to define |
| 44 | CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER. The required parameters are taken from |
| 45 | board configuration and compiled into the host tools atmel_pmecc_params. This |
| 46 | tool will be called in build process to parametrize mkimage for atmelimage |
| 47 | type. The mkimage tool has intentionally _not_ compiled in those parameters. |
| 48 | |
| 49 | The mkimage image type atmelimage also set the 6'th interrupt vector to the |
| 50 | correct value. This feature can also be used to setup a boot.bin for MMC boot. |