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Thomas Abrahame39448e2016-04-23 22:18:13 +05301/*
2 * Configuration settings for the Espresso7420 board.
3 * Copyright (C) 2016 Samsung Electronics
4 * Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __CONFIG_EXYNOS7420_COMMON_H
10#define __CONFIG_EXYNOS7420_COMMON_H
11
12/* High Level Configuration Options */
13#define CONFIG_SAMSUNG /* in a SAMSUNG core */
14#define CONFIG_EXYNOS7420 /* Exynos7 Family */
15#define CONFIG_S5P
16
17#include <asm/arch/cpu.h> /* get chip and board defs */
18#include <linux/sizes.h>
19
20#define CONFIG_ARCH_CPU_INIT
Thomas Abrahame39448e2016-04-23 22:18:13 +053021
22/* Size of malloc() pool before and after relocation */
23#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20))
24
25/* Miscellaneous configurable options */
26#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
27#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
28#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
29
30/* Boot Argument Buffer Size */
31#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
32
33/* select serial console configuration */
Thomas Abrahame39448e2016-04-23 22:18:13 +053034
Thomas Abrahame39448e2016-04-23 22:18:13 +053035/* Timer input clock frequency */
36#define COUNTER_FREQUENCY 24000000
37
38/* Device Tree */
39#define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420"
40
41/* IRAM Layout */
42#define CONFIG_IRAM_BASE 0x02100000
43#define CONFIG_IRAM_SIZE 0x58000
44#define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
Thomas Abraham95e74a32016-11-16 18:49:16 +053045#define CPU_RELEASE_ADDR secondary_boot_addr
Thomas Abrahame39448e2016-04-23 22:18:13 +053046
47/* Number of CPUs available */
48#define CONFIG_CORE_COUNT 0x8
49
50/* select serial console configuration */
Thomas Abrahame39448e2016-04-23 22:18:13 +053051
52#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
53
54#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
55#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
56#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
57#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
58#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
59#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
60#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
61#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
62#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
63#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
64#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
65#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
66#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
67#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
68#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
69#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
70
71/* Configuration of ENV Blocks */
72#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
73
74#define BOOT_TARGET_DEVICES(func) \
75 func(MMC, mmc, 1) \
76 func(MMC, mmc, 0) \
77
78#ifndef MEM_LAYOUT_ENV_SETTINGS
79#define MEM_LAYOUT_ENV_SETTINGS \
80 "bootm_size=0x10000000\0" \
81 "kernel_addr_r=0x42000000\0" \
82 "fdt_addr_r=0x43000000\0" \
83 "ramdisk_addr_r=0x43300000\0" \
84 "scriptaddr=0x50000000\0" \
85 "pxefile_addr_r=0x51000000\0"
86#endif
87
88#ifndef EXYNOS_DEVICE_SETTINGS
89#define EXYNOS_DEVICE_SETTINGS \
90 "stdin=serial\0" \
91 "stdout=serial\0" \
92 "stderr=serial\0"
93#endif
94
95#ifndef EXYNOS_FDTFILE_SETTING
96#define EXYNOS_FDTFILE_SETTING
97#endif
98
99#define CONFIG_EXTRA_ENV_SETTINGS \
100 EXYNOS_DEVICE_SETTINGS \
101 EXYNOS_FDTFILE_SETTING \
102 MEM_LAYOUT_ENV_SETTINGS
103
104#endif /* __CONFIG_EXYNOS7420_COMMON_H */