blob: 33a3f6c88e2cc96672e029a144dbb7f46d84565e [file] [log] [blame]
wdenk5b1d7132002-11-03 00:07:02 +00001/*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/* U-Boot - Startup Code for PowerPC based Embedded Boards
26 *
27 *
28 * The processor starts at 0x00000100 and the code is executed
29 * from flash. The code is organized to be at an other address
wdenk7e780362004-04-08 22:31:29 +000030 * in memory, but as long we don't jump around before relocating,
wdenk5b1d7132002-11-03 00:07:02 +000031 * board_init lies at a quite high address and when the cpu has
32 * jumped there, everything is ok.
33 * This works because the cpu gives the FLASH (CS0) the whole
34 * address space at startup, and board_init lies as a echo of
wdenk7e780362004-04-08 22:31:29 +000035 * the flash somewhere up there in the memory map.
wdenk5b1d7132002-11-03 00:07:02 +000036 *
37 * board_init will change CS0 to be positioned at the correct
38 * address and (s)dram will be positioned at address 0
39 */
40#include <config.h>
41#include <mpc8xx.h>
42#include <version.h>
43
44#define CONFIG_8xx 1 /* needed for Linux kernel header files */
45#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
46
47#include <ppc_asm.tmpl>
48#include <ppc_defs.h>
49
50#include <asm/cache.h>
51#include <asm/mmu.h>
52
53#ifndef CONFIG_IDENT_STRING
54#define CONFIG_IDENT_STRING ""
55#endif
56
57/* We don't want the MMU yet.
58*/
59#undef MSR_KERNEL
60#define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */
61
62/*
63 * Set up GOT: Global Offset Table
64 *
65 * Use r14 to access the GOT
66 */
67 START_GOT
68 GOT_ENTRY(_GOT2_TABLE_)
69 GOT_ENTRY(_FIXUP_TABLE_)
70
71 GOT_ENTRY(_start)
72 GOT_ENTRY(_start_of_vectors)
73 GOT_ENTRY(_end_of_vectors)
74 GOT_ENTRY(transfer_to_handler)
75
wdenk3b57fe02003-05-30 12:48:29 +000076 GOT_ENTRY(__init_end)
wdenk5b1d7132002-11-03 00:07:02 +000077 GOT_ENTRY(_end)
wdenk5d232d02003-05-22 22:52:13 +000078 GOT_ENTRY(__bss_start)
wdenk5b1d7132002-11-03 00:07:02 +000079 END_GOT
80
81/*
82 * r3 - 1st arg to board_init(): IMMP pointer
83 * r4 - 2nd arg to board_init(): boot flag
84 */
85 .text
86 .long 0x27051956 /* U-Boot Magic Number */
87 .globl version_string
88version_string:
89 .ascii U_BOOT_VERSION
90 .ascii " (", __DATE__, " - ", __TIME__, ")"
91 .ascii CONFIG_IDENT_STRING, "\0"
92
93 . = EXC_OFF_SYS_RESET
94 .globl _start
95_start:
96 lis r3, CFG_IMMR@h /* position IMMR */
97 mtspr 638, r3
98 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
99 b boot_cold
100
101 . = EXC_OFF_SYS_RESET + 0x10
102
103 .globl _start_warm
104_start_warm:
105 li r21, BOOTFLAG_WARM /* Software reboot */
106 b boot_warm
107
108boot_cold:
109boot_warm:
110
111 /* Initialize machine status; enable machine check interrupt */
112 /*----------------------------------------------------------------------*/
113 li r3, MSR_KERNEL /* Set ME, RI flags */
114 mtmsr r3
115 mtspr SRR1, r3 /* Make SRR1 match MSR */
116
117 mfspr r3, ICR /* clear Interrupt Cause Register */
118
119 /* Initialize debug port registers */
120 /*----------------------------------------------------------------------*/
121 xor r0, r0, r0 /* Clear R0 */
122 mtspr LCTRL1, r0 /* Initialize debug port regs */
123 mtspr LCTRL2, r0
124 mtspr COUNTA, r0
125 mtspr COUNTB, r0
126
127 /* Reset the caches */
128 /*----------------------------------------------------------------------*/
129
130 mfspr r3, IC_CST /* Clear error bits */
131 mfspr r3, DC_CST
132
133 lis r3, IDC_UNALL@h /* Unlock all */
134 mtspr IC_CST, r3
135 mtspr DC_CST, r3
136
137 lis r3, IDC_INVALL@h /* Invalidate all */
138 mtspr IC_CST, r3
139 mtspr DC_CST, r3
140
141 lis r3, IDC_DISABLE@h /* Disable data cache */
142 mtspr DC_CST, r3
143
144#if !(defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM))
145 /* On IP860 and PCU E,
146 * we cannot enable IC yet
147 */
148 lis r3, IDC_ENABLE@h /* Enable instruction cache */
149#endif
150 mtspr IC_CST, r3
151
152 /* invalidate all tlb's */
153 /*----------------------------------------------------------------------*/
154
155 tlbia
156 isync
157
158 /*
159 * Calculate absolute address in FLASH and jump there
160 *----------------------------------------------------------------------*/
161
162 lis r3, CFG_MONITOR_BASE@h
163 ori r3, r3, CFG_MONITOR_BASE@l
164 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
165 mtlr r3
166 blr
167
168in_flash:
169
170 /* initialize some SPRs that are hard to access from C */
171 /*----------------------------------------------------------------------*/
172
173 lis r3, CFG_IMMR@h /* pass IMMR as arg1 to C routine */
174 ori r1, r3, CFG_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
175 /* Note: R0 is still 0 here */
176 stwu r0, -4(r1) /* clear final stack frame so that */
177 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
178
179 /*
180 * Disable serialized ifetch and show cycles
181 * (i.e. set processor to normal mode).
182 * This is also a silicon bug workaround, see errata
183 */
184
185 li r2, 0x0007
186 mtspr ICTRL, r2
187
188 /* Set up debug mode entry */
189
190 lis r2, CFG_DER@h
191 ori r2, r2, CFG_DER@l
192 mtspr DER, r2
193
194 /* let the C-code set up the rest */
195 /* */
196 /* Be careful to keep code relocatable ! */
197 /*----------------------------------------------------------------------*/
198
199 GET_GOT /* initialize GOT access */
200
201 /* r3: IMMR */
202 bl cpu_init_f /* run low-level CPU init code (from Flash) */
203
204 mr r3, r21
205 /* r3: BOOTFLAG */
206 bl board_init_f /* run 1st part of board init code (from Flash) */
207
208
wdenk5b1d7132002-11-03 00:07:02 +0000209 .globl _start_of_vectors
210_start_of_vectors:
211
212/* Machine check */
213 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
214
215/* Data Storage exception. "Never" generated on the 860. */
216 STD_EXCEPTION(0x300, DataStorage, UnknownException)
217
218/* Instruction Storage exception. "Never" generated on the 860. */
219 STD_EXCEPTION(0x400, InstStorage, UnknownException)
220
221/* External Interrupt exception. */
222 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
223
224/* Alignment exception. */
225 . = 0x600
226Alignment:
227 EXCEPTION_PROLOG
228 mfspr r4,DAR
229 stw r4,_DAR(r21)
230 mfspr r5,DSISR
231 stw r5,_DSISR(r21)
232 addi r3,r1,STACK_FRAME_OVERHEAD
233 li r20,MSR_KERNEL
234 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
235 lwz r6,GOT(transfer_to_handler)
236 mtlr r6
237 blrl
238.L_Alignment:
239 .long AlignmentException - _start + EXC_OFF_SYS_RESET
240 .long int_return - _start + EXC_OFF_SYS_RESET
241
242/* Program check exception */
243 . = 0x700
244ProgramCheck:
245 EXCEPTION_PROLOG
246 addi r3,r1,STACK_FRAME_OVERHEAD
247 li r20,MSR_KERNEL
248 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
249 lwz r6,GOT(transfer_to_handler)
250 mtlr r6
251 blrl
252.L_ProgramCheck:
253 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
254 .long int_return - _start + EXC_OFF_SYS_RESET
255
256 /* No FPU on MPC8xx. This exception is not supposed to happen.
257 */
258 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
259
260 /* I guess we could implement decrementer, and may have
261 * to someday for timekeeping.
262 */
263 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
264 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
265 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
wdenk27b207f2003-07-24 23:38:38 +0000266 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
wdenk5b1d7132002-11-03 00:07:02 +0000267 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
268
269 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
270 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
271
272 /* On the MPC8xx, this is a software emulation interrupt. It occurs
273 * for all unimplemented and illegal instructions.
274 */
275 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
276
277 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
278 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
279 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
280 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
281
282 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
283 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
284 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
285 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
286 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
287 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
288 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
289
290 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
291 STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
292 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
293 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
294
295
296 .globl _end_of_vectors
297_end_of_vectors:
298
299
300 . = 0x2000
301
302/*
303 * This code finishes saving the registers to the exception frame
304 * and jumps to the appropriate handler for the exception.
305 * Register r21 is pointer into trap frame, r1 has new stack pointer.
306 */
307 .globl transfer_to_handler
308transfer_to_handler:
309 stw r22,_NIP(r21)
310 lis r22,MSR_POW@h
311 andc r23,r23,r22
312 stw r23,_MSR(r21)
313 SAVE_GPR(7, r21)
314 SAVE_4GPRS(8, r21)
315 SAVE_8GPRS(12, r21)
316 SAVE_8GPRS(24, r21)
317 mflr r23
318 andi. r24,r23,0x3f00 /* get vector offset */
319 stw r24,TRAP(r21)
320 li r22,0
321 stw r22,RESULT(r21)
322 mtspr SPRG2,r22 /* r1 is now kernel sp */
323 lwz r24,0(r23) /* virtual address of handler */
324 lwz r23,4(r23) /* where to go when done */
325 mtspr SRR0,r24
326 mtspr SRR1,r20
327 mtlr r23
328 SYNC
329 rfi /* jump to handler, enable MMU */
330
331int_return:
332 mfmsr r28 /* Disable interrupts */
333 li r4,0
334 ori r4,r4,MSR_EE
335 andc r28,r28,r4
336 SYNC /* Some chip revs need this... */
337 mtmsr r28
338 SYNC
339 lwz r2,_CTR(r1)
340 lwz r0,_LINK(r1)
341 mtctr r2
342 mtlr r0
343 lwz r2,_XER(r1)
344 lwz r0,_CCR(r1)
345 mtspr XER,r2
346 mtcrf 0xFF,r0
347 REST_10GPRS(3, r1)
348 REST_10GPRS(13, r1)
349 REST_8GPRS(23, r1)
350 REST_GPR(31, r1)
351 lwz r2,_NIP(r1) /* Restore environment */
352 lwz r0,_MSR(r1)
353 mtspr SRR0,r2
354 mtspr SRR1,r0
355 lwz r0,GPR0(r1)
356 lwz r2,GPR2(r1)
357 lwz r1,GPR1(r1)
358 SYNC
359 rfi
360
361/* Cache functions.
362*/
363 .globl icache_enable
364icache_enable:
365 SYNC
366 lis r3, IDC_INVALL@h
367 mtspr IC_CST, r3
368 lis r3, IDC_ENABLE@h
369 mtspr IC_CST, r3
370 blr
371
372 .globl icache_disable
373icache_disable:
374 SYNC
375 lis r3, IDC_DISABLE@h
376 mtspr IC_CST, r3
377 blr
378
379 .globl icache_status
380icache_status:
381 mfspr r3, IC_CST
382 srwi r3, r3, 31 /* >>31 => select bit 0 */
383 blr
384
385 .globl dcache_enable
386dcache_enable:
387#if 0
388 SYNC
389#endif
390#if 1
391 lis r3, 0x0400 /* Set cache mode with MMU off */
392 mtspr MD_CTR, r3
393#endif
394
395 lis r3, IDC_INVALL@h
396 mtspr DC_CST, r3
397#if 0
398 lis r3, DC_SFWT@h
399 mtspr DC_CST, r3
400#endif
401 lis r3, IDC_ENABLE@h
402 mtspr DC_CST, r3
403 blr
404
405 .globl dcache_disable
406dcache_disable:
407 SYNC
408 lis r3, IDC_DISABLE@h
409 mtspr DC_CST, r3
410 lis r3, IDC_INVALL@h
411 mtspr DC_CST, r3
412 blr
413
414 .globl dcache_status
415dcache_status:
416 mfspr r3, DC_CST
417 srwi r3, r3, 31 /* >>31 => select bit 0 */
418 blr
419
420 .globl dc_read
421dc_read:
422 mtspr DC_ADR, r3
423 mfspr r3, DC_DAT
424 blr
425
426/*
427 * unsigned int get_immr (unsigned int mask)
428 *
429 * return (mask ? (IMMR & mask) : IMMR);
430 */
431 .globl get_immr
432get_immr:
433 mr r4,r3 /* save mask */
434 mfspr r3, IMMR /* IMMR */
435 cmpwi 0,r4,0 /* mask != 0 ? */
436 beq 4f
437 and r3,r3,r4 /* IMMR & mask */
4384:
439 blr
440
441 .globl get_pvr
442get_pvr:
443 mfspr r3, PVR
444 blr
445
446
447 .globl wr_ic_cst
448wr_ic_cst:
449 mtspr IC_CST, r3
450 blr
451
452 .globl rd_ic_cst
453rd_ic_cst:
454 mfspr r3, IC_CST
455 blr
456
457 .globl wr_ic_adr
458wr_ic_adr:
459 mtspr IC_ADR, r3
460 blr
461
462
463 .globl wr_dc_cst
464wr_dc_cst:
465 mtspr DC_CST, r3
466 blr
467
468 .globl rd_dc_cst
469rd_dc_cst:
470 mfspr r3, DC_CST
471 blr
472
473 .globl wr_dc_adr
474wr_dc_adr:
475 mtspr DC_ADR, r3
476 blr
477
478/*------------------------------------------------------------------------------*/
479
480/*
481 * void relocate_code (addr_sp, gd, addr_moni)
482 *
483 * This "function" does not return, instead it continues in RAM
484 * after relocating the monitor code.
485 *
486 * r3 = dest
487 * r4 = src
488 * r5 = length in bytes
489 * r6 = cachelinesize
490 */
491 .globl relocate_code
492relocate_code:
493 mr r1, r3 /* Set new stack pointer */
494 mr r9, r4 /* Save copy of Global Data pointer */
495 mr r10, r5 /* Save copy of Destination Address */
496
497 mr r3, r5 /* Destination Address */
498 lis r4, CFG_MONITOR_BASE@h /* Source Address */
499 ori r4, r4, CFG_MONITOR_BASE@l
wdenk3b57fe02003-05-30 12:48:29 +0000500 lwz r5, GOT(__init_end)
501 sub r5, r5, r4
wdenk5b1d7132002-11-03 00:07:02 +0000502 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
503
504 /*
505 * Fix GOT pointer:
506 *
507 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
508 *
509 * Offset:
510 */
511 sub r15, r10, r4
512
513 /* First our own GOT */
514 add r14, r14, r15
wdenkd0fb80c2003-01-11 09:48:40 +0000515 /* then the one used by the C code */
wdenk5b1d7132002-11-03 00:07:02 +0000516 add r30, r30, r15
517
518 /*
519 * Now relocate code
520 */
521
522 cmplw cr1,r3,r4
523 addi r0,r5,3
524 srwi. r0,r0,2
525 beq cr1,4f /* In place copy is not necessary */
526 beq 7f /* Protect against 0 count */
527 mtctr r0
528 bge cr1,2f
529
530 la r8,-4(r4)
531 la r7,-4(r3)
5321: lwzu r0,4(r8)
533 stwu r0,4(r7)
534 bdnz 1b
535 b 4f
536
5372: slwi r0,r0,2
538 add r8,r4,r0
539 add r7,r3,r0
5403: lwzu r0,-4(r8)
541 stwu r0,-4(r7)
542 bdnz 3b
543
544/*
545 * Now flush the cache: note that we must start from a cache aligned
546 * address. Otherwise we might miss one cache line.
547 */
5484: cmpwi r6,0
549 add r5,r3,r5
550 beq 7f /* Always flush prefetch queue in any case */
551 subi r0,r6,1
552 andc r3,r3,r0
553 mr r4,r3
5545: dcbst 0,r4
555 add r4,r4,r6
556 cmplw r4,r5
557 blt 5b
558 sync /* Wait for all dcbst to complete on bus */
559 mr r4,r3
5606: icbi 0,r4
561 add r4,r4,r6
562 cmplw r4,r5
563 blt 6b
5647: sync /* Wait for all icbi to complete on bus */
565 isync
566
567/*
568 * We are done. Do not return, instead branch to second part of board
569 * initialization, now running from RAM.
570 */
571
572 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
573 mtlr r0
574 blr
575
576in_ram:
577
578 /*
579 * Relocation Function, r14 point to got2+0x8000
580 *
wdenk8bde7f72003-06-27 21:31:46 +0000581 * Adjust got2 pointers, no need to check for 0, this code
582 * already puts a few entries in the table.
wdenk5b1d7132002-11-03 00:07:02 +0000583 */
584 li r0,__got2_entries@sectoff@l
585 la r3,GOT(_GOT2_TABLE_)
586 lwz r11,GOT(_GOT2_TABLE_)
587 mtctr r0
588 sub r11,r3,r11
589 addi r3,r3,-4
5901: lwzu r0,4(r3)
591 add r0,r0,r11
592 stw r0,0(r3)
593 bdnz 1b
594
595 /*
wdenk8bde7f72003-06-27 21:31:46 +0000596 * Now adjust the fixups and the pointers to the fixups
wdenk5b1d7132002-11-03 00:07:02 +0000597 * in case we need to move ourselves again.
598 */
5992: li r0,__fixup_entries@sectoff@l
600 lwz r3,GOT(_FIXUP_TABLE_)
601 cmpwi r0,0
602 mtctr r0
603 addi r3,r3,-4
604 beq 4f
6053: lwzu r4,4(r3)
606 lwzux r0,r4,r11
607 add r0,r0,r11
608 stw r10,0(r3)
609 stw r0,0(r4)
610 bdnz 3b
6114:
612clear_bss:
613 /*
614 * Now clear BSS segment
615 */
wdenk5d232d02003-05-22 22:52:13 +0000616 lwz r3,GOT(__bss_start)
wdenk5b1d7132002-11-03 00:07:02 +0000617 lwz r4,GOT(_end)
wdenk5b1d7132002-11-03 00:07:02 +0000618
619 cmplw 0, r3, r4
620 beq 6f
621
622 li r0, 0
6235:
624 stw r0, 0(r3)
625 addi r3, r3, 4
626 cmplw 0, r3, r4
627 bne 5b
6286:
629
630 mr r3, r9 /* Global Data pointer */
631 mr r4, r10 /* Destination Address */
632 bl board_init_r
633
wdenk5b1d7132002-11-03 00:07:02 +0000634 /*
635 * Copy exception vector code to low memory
636 *
637 * r3: dest_addr
638 * r7: source address, r8: end address, r9: target address
639 */
640 .globl trap_init
641trap_init:
642 lwz r7, GOT(_start)
643 lwz r8, GOT(_end_of_vectors)
644
wdenk682011f2003-06-03 23:54:09 +0000645 li r9, 0x100 /* reset vector always at 0x100 */
wdenk5b1d7132002-11-03 00:07:02 +0000646
647 cmplw 0, r7, r8
648 bgelr /* return if r7>=r8 - just in case */
649
650 mflr r4 /* save link register */
6511:
652 lwz r0, 0(r7)
653 stw r0, 0(r9)
654 addi r7, r7, 4
655 addi r9, r9, 4
656 cmplw 0, r7, r8
657 bne 1b
658
659 /*
660 * relocate `hdlr' and `int_return' entries
661 */
662 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
663 li r8, Alignment - _start + EXC_OFF_SYS_RESET
6642:
665 bl trap_reloc
666 addi r7, r7, 0x100 /* next exception vector */
667 cmplw 0, r7, r8
668 blt 2b
669
670 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
671 bl trap_reloc
672
673 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
674 bl trap_reloc
675
676 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
677 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
6783:
679 bl trap_reloc
680 addi r7, r7, 0x100 /* next exception vector */
681 cmplw 0, r7, r8
682 blt 3b
683
684 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
685 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
6864:
687 bl trap_reloc
688 addi r7, r7, 0x100 /* next exception vector */
689 cmplw 0, r7, r8
690 blt 4b
691
692 mtlr r4 /* restore link register */
693 blr
694
695 /*
696 * Function: relocate entries for one exception vector
697 */
698trap_reloc:
699 lwz r0, 0(r7) /* hdlr ... */
700 add r0, r0, r3 /* ... += dest_addr */
701 stw r0, 0(r7)
702
703 lwz r0, 4(r7) /* int_return ... */
704 add r0, r0, r3 /* ... += dest_addr */
705 stw r0, 4(r7)
706
707 sync
708 isync
709
710 blr