Ramneek Mehresh | ba92ee0 | 2015-05-29 14:47:19 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2015 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * FSL USB HOST xHCI Controller |
| 5 | * |
| 6 | * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com> |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 9 | */ |
| 10 | |
| 11 | #include <common.h> |
| 12 | #include <usb.h> |
| 13 | #include <asm-generic/errno.h> |
| 14 | #include <asm/arch-ls102xa/immap_ls102xa.h> |
| 15 | #include <linux/compat.h> |
| 16 | #include <linux/usb/xhci-fsl.h> |
| 17 | #include <linux/usb/dwc3.h> |
| 18 | #include "xhci.h" |
| 19 | |
| 20 | /* Declare global data pointer */ |
| 21 | DECLARE_GLOBAL_DATA_PTR; |
| 22 | |
| 23 | static struct fsl_xhci fsl_xhci; |
| 24 | unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR; |
| 25 | |
| 26 | __weak int __board_usb_init(int index, enum usb_init_type init) |
| 27 | { |
| 28 | return 0; |
| 29 | } |
| 30 | |
| 31 | void usb_phy_reset(struct dwc3 *dwc3_reg) |
| 32 | { |
| 33 | /* Assert USB3 PHY reset */ |
| 34 | setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); |
| 35 | |
| 36 | /* Assert USB2 PHY reset */ |
| 37 | setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); |
| 38 | |
| 39 | mdelay(200); |
| 40 | |
| 41 | /* Clear USB3 PHY reset */ |
| 42 | clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); |
| 43 | |
| 44 | /* Clear USB2 PHY reset */ |
| 45 | clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); |
| 46 | } |
| 47 | |
| 48 | static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci) |
| 49 | { |
| 50 | int ret = 0; |
| 51 | |
| 52 | ret = dwc3_core_init(fsl_xhci->dwc3_reg); |
| 53 | if (ret) { |
| 54 | debug("%s:failed to initialize core\n", __func__); |
| 55 | return ret; |
| 56 | } |
| 57 | |
| 58 | /* We are hard-coding DWC3 core to Host Mode */ |
| 59 | dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); |
| 60 | |
| 61 | return ret; |
| 62 | } |
| 63 | |
| 64 | static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci) |
| 65 | { |
| 66 | /* |
| 67 | * Currently fsl socs do not support PHY shutdown from |
| 68 | * sw. But this support may be added in future socs. |
| 69 | */ |
| 70 | return 0; |
| 71 | } |
| 72 | |
| 73 | int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) |
| 74 | { |
| 75 | struct fsl_xhci *ctx = &fsl_xhci; |
| 76 | int ret = 0; |
| 77 | |
| 78 | ctx->hcd = (struct xhci_hccr *)ctr_addr[index]; |
| 79 | ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); |
| 80 | |
| 81 | ret = board_usb_init(index, USB_INIT_HOST); |
| 82 | if (ret != 0) { |
| 83 | puts("Failed to initialize board for USB\n"); |
| 84 | return ret; |
| 85 | } |
| 86 | |
| 87 | ret = fsl_xhci_core_init(ctx); |
| 88 | if (ret < 0) { |
| 89 | puts("Failed to initialize xhci\n"); |
| 90 | return ret; |
| 91 | } |
| 92 | |
| 93 | *hccr = (struct xhci_hccr *)ctx->hcd; |
Nikhil Badola | 7e5a32f | 2015-06-23 09:17:32 +0530 | [diff] [blame^] | 94 | *hcor = (struct xhci_hcor *)((uintptr_t) *hccr |
Ramneek Mehresh | ba92ee0 | 2015-05-29 14:47:19 +0530 | [diff] [blame] | 95 | + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); |
| 96 | |
Nikhil Badola | 7e5a32f | 2015-06-23 09:17:32 +0530 | [diff] [blame^] | 97 | debug("fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n", |
| 98 | (uintptr_t)*hccr, (uintptr_t)*hcor, |
| 99 | (uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); |
Ramneek Mehresh | ba92ee0 | 2015-05-29 14:47:19 +0530 | [diff] [blame] | 100 | |
| 101 | return ret; |
| 102 | } |
| 103 | |
| 104 | void xhci_hcd_stop(int index) |
| 105 | { |
| 106 | struct fsl_xhci *ctx = &fsl_xhci; |
| 107 | |
| 108 | fsl_xhci_core_exit(ctx); |
| 109 | } |