blob: 645ca6427cf41843f90a8fdcf3c941ae144e83c9 [file] [log] [blame]
Vipin KUMAR5b1b1882010-06-29 10:53:34 +05301/*
2 * (C) Copyright 2010
3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Vipin KUMAR5b1b1882010-06-29 10:53:34 +05306 */
7
8/*
Simon Glass64dcd252015-04-05 16:07:40 -06009 * Designware ethernet IP driver for U-Boot
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053010 */
11
12#include <common.h>
Simon Glass75577ba2015-04-05 16:07:41 -060013#include <dm.h>
Simon Glass64dcd252015-04-05 16:07:40 -060014#include <errno.h>
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053015#include <miiphy.h>
16#include <malloc.h>
Stefan Roeseef760252012-05-07 12:04:25 +020017#include <linux/compiler.h>
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053018#include <linux/err.h>
19#include <asm/io.h>
20#include "designware.h"
21
Simon Glass75577ba2015-04-05 16:07:41 -060022DECLARE_GLOBAL_DATA_PTR;
23
Alexey Brodkin92a190a2014-01-22 20:54:06 +040024#if !defined(CONFIG_PHYLIB)
25# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB"
26#endif
27
28static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
29{
30 struct eth_mac_regs *mac_p = bus->priv;
31 ulong start;
32 u16 miiaddr;
33 int timeout = CONFIG_MDIO_TIMEOUT;
34
35 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
36 ((reg << MIIREGSHIFT) & MII_REGMSK);
37
38 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
39
40 start = get_timer(0);
41 while (get_timer(start) < timeout) {
42 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
43 return readl(&mac_p->miidata);
44 udelay(10);
45 };
46
Simon Glass64dcd252015-04-05 16:07:40 -060047 return -ETIMEDOUT;
Alexey Brodkin92a190a2014-01-22 20:54:06 +040048}
49
50static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
51 u16 val)
52{
53 struct eth_mac_regs *mac_p = bus->priv;
54 ulong start;
55 u16 miiaddr;
Simon Glass64dcd252015-04-05 16:07:40 -060056 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
Alexey Brodkin92a190a2014-01-22 20:54:06 +040057
58 writel(val, &mac_p->miidata);
59 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
60 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
61
62 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
63
64 start = get_timer(0);
65 while (get_timer(start) < timeout) {
66 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
67 ret = 0;
68 break;
69 }
70 udelay(10);
71 };
72
73 return ret;
74}
75
Simon Glass64dcd252015-04-05 16:07:40 -060076static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p)
Alexey Brodkin92a190a2014-01-22 20:54:06 +040077{
78 struct mii_dev *bus = mdio_alloc();
79
80 if (!bus) {
81 printf("Failed to allocate MDIO bus\n");
Simon Glass64dcd252015-04-05 16:07:40 -060082 return -ENOMEM;
Alexey Brodkin92a190a2014-01-22 20:54:06 +040083 }
84
85 bus->read = dw_mdio_read;
86 bus->write = dw_mdio_write;
Simon Glass64dcd252015-04-05 16:07:40 -060087 snprintf(bus->name, sizeof(bus->name), name);
Alexey Brodkin92a190a2014-01-22 20:54:06 +040088
89 bus->priv = (void *)mac_regs_p;
90
91 return mdio_register(bus);
92}
Vipin Kumar13edd172012-03-26 00:09:56 +000093
Simon Glass64dcd252015-04-05 16:07:40 -060094static void tx_descs_init(struct dw_eth_dev *priv)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053095{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053096 struct eth_dma_regs *dma_p = priv->dma_regs_p;
97 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
98 char *txbuffs = &priv->txbuffs[0];
99 struct dmamacdescr *desc_p;
100 u32 idx;
101
102 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
103 desc_p = &desc_table_p[idx];
104 desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
105 desc_p->dmamac_next = &desc_table_p[idx + 1];
106
107#if defined(CONFIG_DW_ALTDESCRIPTOR)
108 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
109 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
110 DESC_TXSTS_TXCHECKINSCTRL | \
111 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
112
113 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
114 desc_p->dmamac_cntl = 0;
115 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
116#else
117 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
118 desc_p->txrx_status = 0;
119#endif
120 }
121
122 /* Correcting the last pointer of the chain */
123 desc_p->dmamac_next = &desc_table_p[0];
124
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400125 /* Flush all Tx buffer descriptors at once */
126 flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
127 (unsigned int)priv->tx_mac_descrtable +
128 sizeof(priv->tx_mac_descrtable));
129
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530130 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
Alexey Brodkin74cb7082014-01-13 13:28:38 +0400131 priv->tx_currdescnum = 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530132}
133
Simon Glass64dcd252015-04-05 16:07:40 -0600134static void rx_descs_init(struct dw_eth_dev *priv)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530135{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530136 struct eth_dma_regs *dma_p = priv->dma_regs_p;
137 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
138 char *rxbuffs = &priv->rxbuffs[0];
139 struct dmamacdescr *desc_p;
140 u32 idx;
141
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400142 /* Before passing buffers to GMAC we need to make sure zeros
143 * written there right after "priv" structure allocation were
144 * flushed into RAM.
145 * Otherwise there's a chance to get some of them flushed in RAM when
146 * GMAC is already pushing data to RAM via DMA. This way incoming from
147 * GMAC data will be corrupted. */
148 flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
149 RX_TOTAL_BUFSIZE);
150
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530151 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
152 desc_p = &desc_table_p[idx];
153 desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
154 desc_p->dmamac_next = &desc_table_p[idx + 1];
155
156 desc_p->dmamac_cntl =
157 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
158 DESC_RXCTRL_RXCHAIN;
159
160 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
161 }
162
163 /* Correcting the last pointer of the chain */
164 desc_p->dmamac_next = &desc_table_p[0];
165
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400166 /* Flush all Rx buffer descriptors at once */
167 flush_dcache_range((unsigned int)priv->rx_mac_descrtable,
168 (unsigned int)priv->rx_mac_descrtable +
169 sizeof(priv->rx_mac_descrtable));
170
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530171 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
Alexey Brodkin74cb7082014-01-13 13:28:38 +0400172 priv->rx_currdescnum = 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530173}
174
Simon Glass64dcd252015-04-05 16:07:40 -0600175static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530176{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530177 struct eth_mac_regs *mac_p = priv->mac_regs_p;
178 u32 macid_lo, macid_hi;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530179
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400180 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
181 (mac_id[3] << 24);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530182 macid_hi = mac_id[4] + (mac_id[5] << 8);
183
184 writel(macid_hi, &mac_p->macaddr0hi);
185 writel(macid_lo, &mac_p->macaddr0lo);
186
187 return 0;
188}
189
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400190static void dw_adjust_link(struct eth_mac_regs *mac_p,
191 struct phy_device *phydev)
192{
193 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
194
195 if (!phydev->link) {
196 printf("%s: No link.\n", phydev->dev->name);
197 return;
198 }
199
200 if (phydev->speed != 1000)
201 conf |= MII_PORTSELECT;
202
203 if (phydev->speed == 100)
204 conf |= FES_100;
205
206 if (phydev->duplex)
207 conf |= FULLDPLXMODE;
208
209 writel(conf, &mac_p->conf);
210
211 printf("Speed: %d, %s duplex%s\n", phydev->speed,
212 (phydev->duplex) ? "full" : "half",
213 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
214}
215
Simon Glass64dcd252015-04-05 16:07:40 -0600216static void _dw_eth_halt(struct dw_eth_dev *priv)
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400217{
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400218 struct eth_mac_regs *mac_p = priv->mac_regs_p;
219 struct eth_dma_regs *dma_p = priv->dma_regs_p;
220
221 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
222 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
223
224 phy_shutdown(priv->phydev);
225}
226
Simon Glass64dcd252015-04-05 16:07:40 -0600227static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530228{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530229 struct eth_mac_regs *mac_p = priv->mac_regs_p;
230 struct eth_dma_regs *dma_p = priv->dma_regs_p;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400231 unsigned int start;
Simon Glass64dcd252015-04-05 16:07:40 -0600232 int ret;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530233
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400234 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
Vipin Kumar13edd172012-03-26 00:09:56 +0000235
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400236 start = get_timer(0);
237 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
Alexey Brodkin875143f2015-01-13 17:10:24 +0300238 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
239 printf("DMA reset timeout\n");
Simon Glass64dcd252015-04-05 16:07:40 -0600240 return -ETIMEDOUT;
Alexey Brodkin875143f2015-01-13 17:10:24 +0300241 }
Stefan Roeseef760252012-05-07 12:04:25 +0200242
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400243 mdelay(100);
244 };
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530245
Bin Mengf3edfd32015-06-15 18:40:19 +0800246 /*
247 * Soft reset above clears HW address registers.
248 * So we have to set it here once again.
249 */
250 _dw_write_hwaddr(priv, enetaddr);
251
Simon Glass64dcd252015-04-05 16:07:40 -0600252 rx_descs_init(priv);
253 tx_descs_init(priv);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530254
Ian Campbell49692c52014-05-08 22:26:35 +0100255 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530256
Sonic Zhangd2279222015-01-29 14:38:50 +0800257#ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400258 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
259 &dma_p->opmode);
Sonic Zhangd2279222015-01-29 14:38:50 +0800260#else
261 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
262 &dma_p->opmode);
263#endif
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530264
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400265 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530266
Sonic Zhang2ddaf132015-01-29 13:37:31 +0800267#ifdef CONFIG_DW_AXI_BURST_LEN
268 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
269#endif
270
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400271 /* Start up the PHY */
Simon Glass64dcd252015-04-05 16:07:40 -0600272 ret = phy_startup(priv->phydev);
273 if (ret) {
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400274 printf("Could not initialize PHY %s\n",
275 priv->phydev->dev->name);
Simon Glass64dcd252015-04-05 16:07:40 -0600276 return ret;
Vipin Kumar9afc1af2012-05-07 13:06:44 +0530277 }
278
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400279 dw_adjust_link(mac_p, priv->phydev);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530280
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400281 if (!priv->phydev->link)
Simon Glass64dcd252015-04-05 16:07:40 -0600282 return -EIO;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530283
Armando Viscontiaa510052012-03-26 00:09:55 +0000284 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530285
286 return 0;
287}
288
Simon Glass64dcd252015-04-05 16:07:40 -0600289static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530290{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530291 struct eth_dma_regs *dma_p = priv->dma_regs_p;
292 u32 desc_num = priv->tx_currdescnum;
293 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
Marek Vasut96cec172014-09-15 01:05:23 +0200294 uint32_t desc_start = (uint32_t)desc_p;
295 uint32_t desc_end = desc_start +
296 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
297 uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
298 uint32_t data_end = data_start +
299 roundup(length, ARCH_DMA_MINALIGN);
Ian Campbell964ea7c2014-05-08 22:26:33 +0100300 /*
301 * Strictly we only need to invalidate the "txrx_status" field
302 * for the following check, but on some platforms we cannot
Marek Vasut96cec172014-09-15 01:05:23 +0200303 * invalidate only 4 bytes, so we flush the entire descriptor,
304 * which is 16 bytes in total. This is safe because the
305 * individual descriptors in the array are each aligned to
306 * ARCH_DMA_MINALIGN and padded appropriately.
Ian Campbell964ea7c2014-05-08 22:26:33 +0100307 */
Marek Vasut96cec172014-09-15 01:05:23 +0200308 invalidate_dcache_range(desc_start, desc_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400309
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530310 /* Check if the descriptor is owned by CPU */
311 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
312 printf("CPU not owner of tx frame\n");
Simon Glass64dcd252015-04-05 16:07:40 -0600313 return -EPERM;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530314 }
315
Marek Vasut96cec172014-09-15 01:05:23 +0200316 memcpy(desc_p->dmamac_addr, packet, length);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530317
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400318 /* Flush data to be sent */
Marek Vasut96cec172014-09-15 01:05:23 +0200319 flush_dcache_range(data_start, data_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400320
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530321#if defined(CONFIG_DW_ALTDESCRIPTOR)
322 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
323 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
324 DESC_TXCTRL_SIZE1MASK;
325
326 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
327 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
328#else
329 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
330 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
331 DESC_TXCTRL_TXFIRST;
332
333 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
334#endif
335
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400336 /* Flush modified buffer descriptor */
Marek Vasut96cec172014-09-15 01:05:23 +0200337 flush_dcache_range(desc_start, desc_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400338
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530339 /* Test the wrap-around condition. */
340 if (++desc_num >= CONFIG_TX_DESCR_NUM)
341 desc_num = 0;
342
343 priv->tx_currdescnum = desc_num;
344
345 /* Start the transmission */
346 writel(POLL_DATA, &dma_p->txpolldemand);
347
348 return 0;
349}
350
Simon Glass75577ba2015-04-05 16:07:41 -0600351static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530352{
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400353 u32 status, desc_num = priv->rx_currdescnum;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530354 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
Simon Glass75577ba2015-04-05 16:07:41 -0600355 int length = -EAGAIN;
Marek Vasut96cec172014-09-15 01:05:23 +0200356 uint32_t desc_start = (uint32_t)desc_p;
357 uint32_t desc_end = desc_start +
358 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
359 uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
360 uint32_t data_end;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530361
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400362 /* Invalidate entire buffer descriptor */
Marek Vasut96cec172014-09-15 01:05:23 +0200363 invalidate_dcache_range(desc_start, desc_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400364
365 status = desc_p->txrx_status;
366
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530367 /* Check if the owner is the CPU */
368 if (!(status & DESC_RXSTS_OWNBYDMA)) {
369
370 length = (status & DESC_RXSTS_FRMLENMSK) >> \
371 DESC_RXSTS_FRMLENSHFT;
372
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400373 /* Invalidate received data */
Marek Vasut96cec172014-09-15 01:05:23 +0200374 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
375 invalidate_dcache_range(data_start, data_end);
Simon Glass75577ba2015-04-05 16:07:41 -0600376 *packetp = desc_p->dmamac_addr;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530377 }
378
Simon Glass75577ba2015-04-05 16:07:41 -0600379 return length;
380}
381
382static int _dw_free_pkt(struct dw_eth_dev *priv)
383{
384 u32 desc_num = priv->rx_currdescnum;
385 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
386 uint32_t desc_start = (uint32_t)desc_p;
387 uint32_t desc_end = desc_start +
388 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
389
390 /*
391 * Make the current descriptor valid again and go to
392 * the next one
393 */
394 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
395
396 /* Flush only status field - others weren't changed */
397 flush_dcache_range(desc_start, desc_end);
398
399 /* Test the wrap-around condition. */
400 if (++desc_num >= CONFIG_RX_DESCR_NUM)
401 desc_num = 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530402 priv->rx_currdescnum = desc_num;
403
Simon Glass75577ba2015-04-05 16:07:41 -0600404 return 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530405}
406
Simon Glass64dcd252015-04-05 16:07:40 -0600407static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530408{
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400409 struct phy_device *phydev;
410 int mask = 0xffffffff;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530411
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400412#ifdef CONFIG_PHY_ADDR
413 mask = 1 << CONFIG_PHY_ADDR;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530414#endif
415
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400416 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
417 if (!phydev)
Simon Glass64dcd252015-04-05 16:07:40 -0600418 return -ENODEV;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530419
Ian Campbell15e82e52014-04-28 20:14:05 +0100420 phy_connect_dev(phydev, dev);
421
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400422 phydev->supported &= PHY_GBIT_FEATURES;
423 phydev->advertising = phydev->supported;
424
425 priv->phydev = phydev;
426 phy_config(phydev);
427
Simon Glass64dcd252015-04-05 16:07:40 -0600428 return 0;
429}
430
Simon Glass75577ba2015-04-05 16:07:41 -0600431#ifndef CONFIG_DM_ETH
Simon Glass64dcd252015-04-05 16:07:40 -0600432static int dw_eth_init(struct eth_device *dev, bd_t *bis)
433{
434 return _dw_eth_init(dev->priv, dev->enetaddr);
435}
436
437static int dw_eth_send(struct eth_device *dev, void *packet, int length)
438{
439 return _dw_eth_send(dev->priv, packet, length);
440}
441
442static int dw_eth_recv(struct eth_device *dev)
443{
Simon Glass75577ba2015-04-05 16:07:41 -0600444 uchar *packet;
445 int length;
446
447 length = _dw_eth_recv(dev->priv, &packet);
448 if (length == -EAGAIN)
449 return 0;
450 net_process_received_packet(packet, length);
451
452 _dw_free_pkt(dev->priv);
453
454 return 0;
Simon Glass64dcd252015-04-05 16:07:40 -0600455}
456
457static void dw_eth_halt(struct eth_device *dev)
458{
459 return _dw_eth_halt(dev->priv);
460}
461
462static int dw_write_hwaddr(struct eth_device *dev)
463{
464 return _dw_write_hwaddr(dev->priv, dev->enetaddr);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530465}
466
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400467int designware_initialize(ulong base_addr, u32 interface)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530468{
469 struct eth_device *dev;
470 struct dw_eth_dev *priv;
471
472 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
473 if (!dev)
474 return -ENOMEM;
475
476 /*
477 * Since the priv structure contains the descriptors which need a strict
478 * buswidth alignment, memalign is used to allocate memory
479 */
Ian Campbell1c848a22014-05-08 22:26:32 +0100480 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
481 sizeof(struct dw_eth_dev));
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530482 if (!priv) {
483 free(dev);
484 return -ENOMEM;
485 }
486
487 memset(dev, 0, sizeof(struct eth_device));
488 memset(priv, 0, sizeof(struct dw_eth_dev));
489
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400490 sprintf(dev->name, "dwmac.%lx", base_addr);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530491 dev->iobase = (int)base_addr;
492 dev->priv = priv;
493
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530494 priv->dev = dev;
495 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
496 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
497 DW_DMA_BASE_OFFSET);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530498
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530499 dev->init = dw_eth_init;
500 dev->send = dw_eth_send;
501 dev->recv = dw_eth_recv;
502 dev->halt = dw_eth_halt;
503 dev->write_hwaddr = dw_write_hwaddr;
504
505 eth_register(dev);
506
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400507 priv->interface = interface;
508
509 dw_mdio_init(dev->name, priv->mac_regs_p);
510 priv->bus = miiphy_get_dev_by_name(dev->name);
511
Simon Glass64dcd252015-04-05 16:07:40 -0600512 return dw_phy_init(priv, dev);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530513}
Simon Glass75577ba2015-04-05 16:07:41 -0600514#endif
515
516#ifdef CONFIG_DM_ETH
517static int designware_eth_start(struct udevice *dev)
518{
519 struct eth_pdata *pdata = dev_get_platdata(dev);
520
521 return _dw_eth_init(dev->priv, pdata->enetaddr);
522}
523
524static int designware_eth_send(struct udevice *dev, void *packet, int length)
525{
526 struct dw_eth_dev *priv = dev_get_priv(dev);
527
528 return _dw_eth_send(priv, packet, length);
529}
530
531static int designware_eth_recv(struct udevice *dev, uchar **packetp)
532{
533 struct dw_eth_dev *priv = dev_get_priv(dev);
534
535 return _dw_eth_recv(priv, packetp);
536}
537
538static int designware_eth_free_pkt(struct udevice *dev, uchar *packet,
539 int length)
540{
541 struct dw_eth_dev *priv = dev_get_priv(dev);
542
543 return _dw_free_pkt(priv);
544}
545
546static void designware_eth_stop(struct udevice *dev)
547{
548 struct dw_eth_dev *priv = dev_get_priv(dev);
549
550 return _dw_eth_halt(priv);
551}
552
553static int designware_eth_write_hwaddr(struct udevice *dev)
554{
555 struct eth_pdata *pdata = dev_get_platdata(dev);
556 struct dw_eth_dev *priv = dev_get_priv(dev);
557
558 return _dw_write_hwaddr(priv, pdata->enetaddr);
559}
560
561static int designware_eth_probe(struct udevice *dev)
562{
563 struct eth_pdata *pdata = dev_get_platdata(dev);
564 struct dw_eth_dev *priv = dev_get_priv(dev);
565 int ret;
566
567 debug("%s, iobase=%lx, priv=%p\n", __func__, pdata->iobase, priv);
568 priv->mac_regs_p = (struct eth_mac_regs *)pdata->iobase;
569 priv->dma_regs_p = (struct eth_dma_regs *)(pdata->iobase +
570 DW_DMA_BASE_OFFSET);
571 priv->interface = pdata->phy_interface;
572
573 dw_mdio_init(dev->name, priv->mac_regs_p);
574 priv->bus = miiphy_get_dev_by_name(dev->name);
575
576 ret = dw_phy_init(priv, dev);
577 debug("%s, ret=%d\n", __func__, ret);
578
579 return ret;
580}
581
582static const struct eth_ops designware_eth_ops = {
583 .start = designware_eth_start,
584 .send = designware_eth_send,
585 .recv = designware_eth_recv,
586 .free_pkt = designware_eth_free_pkt,
587 .stop = designware_eth_stop,
588 .write_hwaddr = designware_eth_write_hwaddr,
589};
590
591static int designware_eth_ofdata_to_platdata(struct udevice *dev)
592{
593 struct eth_pdata *pdata = dev_get_platdata(dev);
594 const char *phy_mode;
595
596 pdata->iobase = dev_get_addr(dev);
597 pdata->phy_interface = -1;
598 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
599 if (phy_mode)
600 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
601 if (pdata->phy_interface == -1) {
602 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
603 return -EINVAL;
604 }
605
606 return 0;
607}
608
609static const struct udevice_id designware_eth_ids[] = {
610 { .compatible = "allwinner,sun7i-a20-gmac" },
611 { }
612};
613
614U_BOOT_DRIVER(eth_sandbox) = {
615 .name = "eth_designware",
616 .id = UCLASS_ETH,
617 .of_match = designware_eth_ids,
618 .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
619 .probe = designware_eth_probe,
620 .ops = &designware_eth_ops,
621 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
622 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
623 .flags = DM_FLAG_ALLOC_PRIV_DMA,
624};
625#endif